CMOS PRESETTABLE UP/DOWN COUNTER

文件：1.03602 Mbytes 頁(yè)數(shù)：18 Pages

TI

德州儀器

CMOS PRESETTABLE UP/DOWN COUNTER

文件：302.49 Kbytes 頁(yè)數(shù)：7 Pages

TI

德州儀器

CMOS PRESETTABLE UP/DOWN COUNTER

文件：1.03602 Mbytes 頁(yè)數(shù)：18 Pages

TI

德州儀器

CMOS PRESETTABLE UP/DOWN COUNTER

文件：302.49 Kbytes 頁(yè)數(shù)：7 Pages

TI

德州儀器

CMOS 可預(yù)置加/減計(jì)數(shù)器

CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\\ (CLOCK ENABLE\\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT ? Medium-speed operation… 8 MHz (typ.) @ CL = 50 pF and VDD–VSS = 10 V\n? \"Preset Enable\" and individual \"Jam\" inputs provided\n? BCD outputs in decade mode\n? 5-V, 10-V, and 15-V parametric ratings\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and ;

TI

德州儀器

CMOS 可預(yù)置加/減計(jì)數(shù)器

CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\\ (CLOCK ENABLE\\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT ? Medium-speed operation… 8 MHz (typ.) @ CL = 50 pF and VDD–VSS = 10 V\n? \"Preset Enable\" and individual \"Jam\" inputs provided\n? BCD outputs in decade mode\n? 5-V, 10-V, and 15-V parametric ratings\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and ;

TI

德州儀器

CMOS Presettable Up/Down Counter

CD4029BMS consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY-OUT ? High-Voltage Type (20V Rating) \n? Medium Speed Operation: 8MHz (Typ.) at CL = 50pF and VDD - VSS = 10V \n? Multi-Package Parallel Clocking for Synchronous High Speed Output Response or Ripple Clocking for Slow Clock Input Rise and Fall Times \n? \"Preset Enable\" and Individual \"Jam\" Inputs Pro;

Renesas

瑞薩

Package：16-DIP（0.300"，7.62mm）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 計(jì)數(shù)器，除法器 描述：IC PRESET UP/DWN COUNTER 16-DIP

TI

德州儀器

Package：16-DIP（0.300"，7.62mm）；包裝：管件 類別：集成電路（IC） 計(jì)數(shù)器，除法器 描述：IC PRESET UP/DWN COUNTER 16-DIP

TI

德州儀器

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 計(jì)數(shù)器，除法器 描述：IC PRESET UP/DWN COUNTER 16-SOIC

TI

德州儀器