Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

Synchronous up/down counter, binary/decade counter

DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input

文件：188.66 Kbytes 頁數(shù)：14 Pages

PHI

PHI

IC Reference Design Transformers

文件：96.18 Kbytes 頁數(shù)：2 Pages

ICE

Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS

Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The IW4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE,

文件：371.33 Kbytes 頁數(shù)：8 Pages

INTEGRAL

Integral Corp.