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          首頁
                >CD4029B>規(guī)格書列表
                
          
            
          
                
          
                    
          型號下載 訂購功能描述制造商 上傳企業(yè)LOGO
          
                    
          CD4029B
          CMOS Presettable Up/Down Counter
          
Features:
? Medium-speed operation . . . 8 MHz (typ.)
@Cy_ = 50 pF and Vpp—Vgg = 10 V
# Multi-package parallel clocking for synchronous
high speed output response or ripple clocking
for slow clock input rise and fall times
= “Preset Enable” and individual “Jam” inputs provided
? Binary or d
          文件：1.02221 Mbytes 頁數(shù)：22 Pages
          TI
          德州儀器
          

          CD4029B
          CMOS PRESETTABLE UP/DOWN COUNTER
          文件：302.49 Kbytes 頁數(shù)：7 Pages
          TI
          德州儀器
          

          CD4029B
          CMOS PRESETTABLE UP/DOWN COUNTER
          文件：1.03602 Mbytes 頁數(shù)：18 Pages
          TI
          德州儀器
          

          CD4029BNSR
          絲印：CD4029B；Package：SOP；CMOS Presettable Up/Down Counter
          
Features:
? Medium-speed operation . . . 8 MHz (typ.)
@Cy_ = 50 pF and Vpp—Vgg = 10 V
# Multi-package parallel clocking for synchronous
high speed output response or ripple clocking
for slow clock input rise and fall times
= “Preset Enable” and individual “Jam” inputs provided
? Binary or d
          文件：1.02221 Mbytes 頁數(shù)：22 Pages
          TI
          德州儀器
          

          CD4029BNSR.A
          絲印：CD4029B；Package：SOP；CMOS Presettable Up/Down Counter
          
Features:
? Medium-speed operation . . . 8 MHz (typ.)
@Cy_ = 50 pF and Vpp—Vgg = 10 V
# Multi-package parallel clocking for synchronous
high speed output response or ripple clocking
for slow clock input rise and fall times
= “Preset Enable” and individual “Jam” inputs provided
? Binary or d
          文件：1.02221 Mbytes 頁數(shù)：22 Pages
          TI
          德州儀器
          

          CD4029BC
          Presettable Binary/Decade Up/Down Counter
          
General Description

The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte
          文件：94.49 Kbytes 頁數(shù)：8 Pages
          FAIRCHILD
          仙童半導(dǎo)體
          

          CD4029BCN
          Presettable Binary/Decade Up/Down Counter
          
General Description

The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte
          文件：94.49 Kbytes 頁數(shù)：8 Pages
          FAIRCHILD
          仙童半導(dǎo)體
          

          CD4029BCSJ
          Presettable Binary/Decade Up/Down Counter
          
General Description

The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte
          文件：94.49 Kbytes 頁數(shù)：8 Pages
          FAIRCHILD
          仙童半導(dǎo)體
          

          CD4029BCWM
          Presettable Binary/Decade Up/Down Counter
          
General Description

The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte
          文件：94.49 Kbytes 頁數(shù)：8 Pages
          FAIRCHILD
          仙童半導(dǎo)體
          

          CD4029BE
          絲?。?a target="_blank" title="Marking" href="/cd4029be/marking.html">CD4029BE；Package：PDIP；CMOS Presettable Up/Down Counter
          
Features:
? Medium-speed operation . . . 8 MHz (typ.)
@Cy_ = 50 pF and Vpp—Vgg = 10 V
# Multi-package parallel clocking for synchronous
high speed output response or ripple clocking
for slow clock input rise and fall times
= “Preset Enable” and individual “Jam” inputs provided
? Binary or d
          文件：1.02221 Mbytes 頁數(shù)：22 Pages
          TI
          德州儀器
          

          
            
          
		
        
          
            
          
                
          替換型號
          
            
          
            
            
        
          
		
        
          
            
          
                
          技術(shù)參數(shù)
          
            
          
            
            
            	
          • Bits (#)：
            4
          • Technology Family：
            CD4000
          • Supply voltage (Min) (V)：
            3
          • Supply voltage (Max) (V)：
            18
          • Input type：
            Standard CMOS
          • Output type：
            Push-Pull
          • Features：
            Balanced outputs
          
            
          
        
          
            
          供應(yīng)商型號品牌批號封裝庫存備注價格
          
                
          



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          25+
          		

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詢價
          

          



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          更多CD4029B供應(yīng)商
            更新時間2026-1-18 11:09:00
        
          
        
          
          
          
            
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