PROGRAMMABLE DELAY CHIP

Description The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic symbol. The first two

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PROGRAMMABLE DELAY CHIP

Description The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elem

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5V ECL Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

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5V ECL Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

文件：64.9 Kbytes 頁(yè)數(shù)：8 Pages

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Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

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Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

文件：121.52 Kbytes 頁(yè)數(shù)：8 Pages

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5V ECL Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

文件：64.9 Kbytes 頁(yè)數(shù)：8 Pages

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1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP

The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The 100 Series contains temperature compensation. ? Guaranteed Low Skew Specification ? Synchronous Enabling/Disabling ? Multiplexed Clock Inputs ? VBB Output for Single-Ended U

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3-BIT SCANNABLE REGISTERED ADDRESS DRIVER

The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed

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8-BIT SCANABLE REGISTER

5V ECL 8-Bit Scannable Register The MC10E/100E241 is an 8-bit shiftable register. Unlike a standard universal shift register such as the E141, the E241 features internal data feedback organized so that the SHIFT control overrides the HOLD/LOAD control. This enables the normal operations of HOLD a

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