9-BIT HOLD REGISTER

Description The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 ? D8 accepting parallel input data. The SEL (Select) input pin is used to switch between the two modes of operation ?

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6-BIT D LATCH

Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset

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6-BIT D REGISTER

Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs g

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5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

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5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

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6-BIT 2:1 MUX-LATCH

Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single?ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

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3-BIT 4:1 MUX-LATCH

Description The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LE

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QUAD 2:1 MULTIPLEXER

Description The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. The 100 Series contains temperature compensation.

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QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. ? Individual Select Controls ? 550ps Max. D to Output ? 80

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QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. ? Individual Select Controls ? 550ps Max. D to Output ? 80

文件：99.46 Kbytes 頁數(shù)：4 Pages

MOTOROLA

摩托羅拉