QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. ? Individual Select Controls ? 550ps Max. D to Output ? 80

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摩托羅拉

5-BIT 2:1 MULTIPLEXER

Description The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input (SEL). The 100 Series contains temperature compensation. Features ? 600 ps Max. D to Output ? 800 ps Max. SEL to Output ? Differential Outputs ? One VCC

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12-BIT PARITY GENERATOR/CHECKER

The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The 100 Series contains temperature compensation. ? Provides Odd-HIGH Parity of 12 Inputs ? Shiftable Output Register with

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2-BIT 8:1 MULTIPLEXER

Description The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs (SEL0, 1, 2) control which one of the eight data inputs (A0 ? A7, B0 ? B7) is propagated to the output. The 100 Series contains temperature compensation. Features ?

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16:1 MULTIPLEXER

Description The MC10E/100E164 is a 16:1 multiplexer with a differential output. The select inputs (SEL0, 1, 2, 3 ) control which one of the sixteen data inputs (A0 ? A15) is propagated to the output. Special attention to the design layout results in a typical skew between the 16 inputs of only 5

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9-BIT MAGNITUDE COMPARATOR

Description The MC10E/100E166 is a 9-bit magnitude comparator which compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other. The 100 Series contains temperature compensation Features ? 1100 ps Max. A = B ? PECL Mode Operating Range:

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6-BIT 2:1 MUX-REGISTER

Description The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (

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3-BIT 4:1 MULTIPLEXER

Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs (see logic symbol). The three Select inputs control which one of the four data inputs in each case is propagated to the corresponding output

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9-BIT LATCH WITH PARITY

Description The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type se

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ERROR DETECTION/ CORRECTION CIRCUIT

The MC10E/100E193 is an error detection and correction (EDAC) circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also provided at the PGEN pin, after Odd/Even

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