Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

文件：64.709 Kbytes 頁數(shù)：5 Pages

PHI

PHI

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

文件：64.709 Kbytes 頁數(shù)：5 Pages

PHI

PHI

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

文件：64.709 Kbytes 頁數(shù)：5 Pages

PHI

PHI

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

文件：64.709 Kbytes 頁數(shù)：5 Pages

PHI

PHI

DUAL-J-K MASTER-SLAVE FLIP-FLOP

DESCRIPTION The HCC4027B (extended temperature range) and HCF4027B (intermediate temperature range) are monolithic integrated circuit, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. ■ SET-RESET CAPABILITY ■ STATIC FLIP-FLOP OPERATION - RETAINS

文件：286.35 Kbytes 頁數(shù)：12 Pages

STMICROELECTRONICS

意法半導(dǎo)體

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

文件：531 Kbytes 頁數(shù)：12 Pages

TI

德州儀器