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          首頁 >HEF4040B>規(guī)格書列表

          型號(hào)下載 訂購功能描述制造商 上傳企業(yè)LOGO

          HEF4040B

          12-stage binary counter

          DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

          文件:42.85 Kbytes 頁數(shù):5 Pages

          PHI

          PHI

          PHI

          HEF4040B

          12-stage binary ripple counter

          1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

          文件:211.97 Kbytes 頁數(shù):11 Pages

          NEXPERIA

          安世

          HEF4040BD

          12-stage binary counter

          DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

          文件:42.85 Kbytes 頁數(shù):5 Pages

          PHI

          PHI

          PHI

          HEF4040BF

          12-stage binary counter

          DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

          文件:42.85 Kbytes 頁數(shù):5 Pages

          PHI

          PHI

          PHI

          HEF4040BN

          12-stage binary counter

          DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

          文件:42.85 Kbytes 頁數(shù):5 Pages

          PHI

          PHI

          PHI

          HEF4040BP

          12-stage binary counter

          DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

          文件:42.85 Kbytes 頁數(shù):5 Pages

          PHI

          PHI

          PHI

          HEF4040B-Q100

          12-stage binary ripple counter

          1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

          文件:212.39 Kbytes 頁數(shù):11 Pages

          NEXPERIA

          安世

          HEF4040B-Q100_V01

          12-stage binary ripple counter

          1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

          文件:212.39 Kbytes 頁數(shù):11 Pages

          NEXPERIA

          安世

          HEF4040BT

          12-stage binary ripple counter

          1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

          文件:211.97 Kbytes 頁數(shù):11 Pages

          NEXPERIA

          安世

          HEF4040BT

          12-stage binary counter

          DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

          文件:42.85 Kbytes 頁數(shù):5 Pages

          PHI

          PHI

          PHI

          技術(shù)參數(shù)

          • VCC (V):

            3.0?-?15

          • Output drive capability (mA):

            ± 2.4

          • Logic switching levels:

            CMOS

          • tpd (ns):

            35

          • Power dissipation considerations:

            medium

          • Tamb (°C):

            -40~85

          • Rth(j-a) (K/W):

            78

          • Ψth(j-top) (K/W):

            3.5

          • Rth(j-c) (K/W):

            36.9

          • Package name:

            SO16

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          更多HEF4040B供應(yīng)商 更新時(shí)間2026-1-18 15:35:00
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