64-stage static shift register

DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL lo

文件：76.29 Kbytes 頁數：7 Pages

PHI

PHI

64-stage static shift register

DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL lo

文件：76.29 Kbytes 頁數：7 Pages

PHI

PHI

64-stage static shift register

DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL lo

文件：76.29 Kbytes 頁數：7 Pages

PHI

PHI

64-stage static shift register

DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL lo

文件：76.29 Kbytes 頁數：7 Pages

PHI

PHI

64-stage static shift register

DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL lo

文件：76.29 Kbytes 頁數：7 Pages

PHI

PHI

64-stage static shift register

DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL lo

文件：76.29 Kbytes 頁數：7 Pages

PHI

PHI

64-stage static shift register

DESCRIPTION The HEF4031B is an edge-triggered 64-stage static shift register with two serial data inputs (DA, DB), a data select input A/B, a clock input (CP), a buffered clock output (CO), and buffered outputs from the 64th bit position (O63, O63). The output O63 is capable of driving one TTL lo

文件：76.29 Kbytes 頁數：7 Pages

PHI

PHI

64-stage static shift register

恩XP