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                >HEF4030BT>規(guī)格書(shū)列表
                
          
            
          
                
          
                    
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          HEF4030BT
          Quadruple exclusive-OR gate
          
DESCRIPTION
The HEF4030B provides the positive quadruple exclusive-OR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.
   
          文件：28.19 Kbytes 頁(yè)數(shù)：3 Pages
          PHI
          PHI
          PHI
          

          HEF4030BT
          Quad 2-input EXCLUSIVE-OR gate
          
1. General description
The HEF4030B is a quad 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes. This enables
the use of current limiting resistors to interface inputs to voltages in excess of VDD.
2. Features and benefits
? Wide supply voltage range from 3.0 V to 15.0 V
? CMOS low power
          文件：198.68 Kbytes 頁(yè)數(shù)：10 Pages
          NEXPERIA
          安世
          

          HEF4030BT
          Quad 2-input EXCLUSIVE-OR gate
          文件：115.56 Kbytes 頁(yè)數(shù)：12 Pages
          恩XP
          恩XP
          

          HEF4030BT-Q100
          Quad 2-input EXCLUSIVE-OR gate
          
1. General description
The HEF4030B-Q100 is a quad 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q1
          文件：198.76 Kbytes 頁(yè)數(shù)：10 Pages
          NEXPERIA
          安世
          

          HEF4030BT653
          Quad 2-input EXCLUSIVE-OR gate
          文件：115.56 Kbytes 頁(yè)數(shù)：12 Pages
          恩XP
          恩XP
          

          HEF4030BT-Q100
          Quad 2-input EXCLUSIVE-OR gate
          文件：678.15 Kbytes 頁(yè)數(shù)：11 Pages
          NEXPERIA
          安世
          

          HEF4030BT
          Quad 2-input EXCLUSIVE-OR gate
          The HEF4030B is a quad 2?input EXCLUSIVE?OR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.\n    It operates over a recommended VDD power supply range of 3V to 15 V referenced to VSS (usually ground). Unused inputs must be connected   ? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from -40°C to +125°C\n? Complies with JEDEC standard JESD 13-B\n? Inputs and outputs are protected against electrostatic effects;
          Nexperia
          安世
          

          HEF4030BT-Q100
          Quad 2-input EXCLUSIVE-OR gate
          The HEF4030B-Q100 is a quad 2-input EXCLUSIVE-OR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.\n    It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connec  ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40°C to +85°C and from -40°C to +125°C\n\n? Fully static operation\n? 5 V, 10 V, and 15 V parametric ratings\n? Standardized symmetrical output characteristics\n? ESD protection:? MIL-STD-833, method 3015 excee;
          Nexperia
          安世
          

          HEF4030BT,652
          Package：14-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類(lèi)別：集成電路（IC） 門(mén)和反相器 描述：IC GATE XOR 4CH 2-INP 14SO
          Nexperia USA Inc.
          Nexperia USA Inc.
          

          HEF4030BT,653
          Package：14-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類(lèi)別：集成電路（IC） 門(mén)和反相器 描述：IC GATE XOR 4CH 2-INP 14SO
          Nexperia USA Inc.
          Nexperia USA Inc.
          

          
            
          
		
        
          
            
          
                
          技術(shù)參數(shù)
          
            
          
            
            
            	
          • VCC (V)：
            3.0?-?15
          • Logic switching levels：
            CMOS
          • Output drive capability (mA)：
            ± 2.4
          • tpd (ns)：
            30
          • fmax (MHz)：
            10
          • Nr of bits：
            4
          • Power dissipation considerations：
            medium
          • Tamb (°C)：
            -40~85
          • Rth(j-a) (K/W)：
            88
          • Ψth(j-top) (K/W)：
            6.7
          • Rth(j-c) (K/W)：
            45
          • Package name：
            SO14
          
            
          
        
          
            
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            更新時(shí)間2026-1-18 14:14:00
        
          
        
          
          
          
            
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