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          首頁(yè) >CD4027B>規(guī)格書(shū)列表

          型號(hào)下載 訂購(gòu)功能描述制造商 上傳企業(yè)LOGO

          CD4027B

          CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

          文件:531 Kbytes 頁(yè)數(shù):12 Pages

          TI

          德州儀器

          CD4027B

          CMOS Dual J-K Master-Slave Flip-Flop

          文件:1.51688 Mbytes 頁(yè)數(shù):27 Pages

          TI

          德州儀器

          CD4027BCM

          Dual J-K Master/Slave Flip-Flop with Set and Reset

          General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edg

          文件:68.79 Kbytes 頁(yè)數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          CD4027BCN

          Dual J-K Master/Slave Flip-Flop with Set and Reset

          General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edg

          文件:68.79 Kbytes 頁(yè)數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          CD4027BMS

          CMOS Dual J-K Master-Slave Flip-Flop

          Description CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-out

          文件:72.39 Kbytes 頁(yè)數(shù):8 Pages

          INTERSIL

          CD4027BMS

          CMOS Dual J-KMaster-Slave Flip-Flop

          Features ? High Voltage Type (20V Rating) ? Set - Reset Capability ? Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low” ? Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V ? Standardized Symmetrical Output Characteristics ? 100 Test

          文件:337.81 Kbytes 頁(yè)數(shù):8 Pages

          RENESAS

          瑞薩

          CD4027B_07

          CMOS Dual J-K Master-Slave Flip-Flop

          文件:676.57 Kbytes 頁(yè)數(shù):14 Pages

          TI

          德州儀器

          CD4027B_15

          CMOS Dual J-K Master-Slave Flip-Flop

          文件:1.51688 Mbytes 頁(yè)數(shù):27 Pages

          TI

          德州儀器

          CD4027BC

          Dual J-K Master/Slave Flip-Flop with Set and Reset

          文件:125.45 Kbytes 頁(yè)數(shù):6 Pages

          NSC

          國(guó)半

          CD4027BE

          CMOS Dual J-K Master-Slave Flip-Flop

          文件:1.51688 Mbytes 頁(yè)數(shù):27 Pages

          TI

          德州儀器

          技術(shù)參數(shù)

          • Technology Family:

            CD4000

          • Supply voltage (Min) (V):

            3

          • Supply voltage (Max) (V):

            18

          • Input type:

            TTL

          • Output type:

            Push-Pull

          • Clock Frequency (MHz):

            12

          • ICC (Max) (uA):

            600

          • IOL (Max) (mA):

            1.5

          • IOH (Max) (mA):

            -1.5

          • Features:

            Balanced outputs

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          更多CD4027B供應(yīng)商 更新時(shí)間2026-1-18 16:30:00
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