Dual J-K Master/Slave Flip-Flop with Set and Reset

文件：125.45 Kbytes 頁數(shù)：6 Pages

NSC

國半

Dual J-K Master/Slave Flip-Flop with Set and Reset

General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edg

文件：68.79 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Dual J-K Master/Slave Flip-Flop with Set and Reset

General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edg

文件：68.79 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Dual J-K Master/Slave Flip-Flop with Set and Reset

ONSEMI

安森美半導(dǎo)體

Package：16-DIP（0.300"，7.62mm）；包裝：管件 功能：設(shè)置（預(yù)設(shè)）和復(fù)位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF JK TYPE DUAL 1BIT 16DIP

ONSEMI

安森美半導(dǎo)體