CMOS Dual J-K Master-Slave Flip-Flop

Description CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-out

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CMOS Dual J-KMaster-Slave Flip-Flop

Features ? High Voltage Type (20V Rating) ? Set - Reset Capability ? Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low” ? Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V ? Standardized Symmetrical Output Characteristics ? 100 Test

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CMOS Dual J-K Master-Slave Flip-Flop

CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement ? High Voltage Type (20V Rating) \n? Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either \"High\" or \"Low\" \n? Standardized Symmetrical Output Characteristics \n? Maximum Input Current of 1μA at 18V Over Full Package-Temperature Range; \n? Noise Margin (Over Full Packag;

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CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

文件：531 Kbytes 頁數(shù)：12 Pages

TI

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CMOS Dual J-K Master-Slave Flip-Flop

文件：676.57 Kbytes 頁數(shù)：14 Pages

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CMOS Dual J-K Master-Slave Flip-Flop

文件：1.51688 Mbytes 頁數(shù)：27 Pages

TI

德州儀器