CMOS Dual J-K Master-Slave Flip-Flop

Description CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-out

文件：72.39 Kbytes 頁數(shù)：8 Pages

INTERSIL

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

文件：531 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

SEMICONDUCTORS

文件：2.43533 Mbytes 頁數(shù)：31 Pages

ETCList of Unclassifed Manufacturers

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CMOS Dual J-K Master-Slave Flip-Flop

Description\nCD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-outpu ? High Voltage Type (20V Rating)\n? Set - Reset Capability\n? Static Flip-Flop Operation - Retains State Indefinitely\n?? with Clock Level Either “High” or “Low”\n? Medium Speed Operation - 16MHz (typ.) Clock Toggle\n?? Rate at 10V\n? Standardized Symmetrical Output Characteristics\n? 100% Teste;

Renesas

瑞薩

2路JK觸發(fā)器

The CD4027 is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q(—)). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct ( ? Wide supply voltage range from 3V to 15V\n? Fully static operation\n? 5V, 10V, and 15V parametric ratings\n? Standardized symmetrical output characteristics\n? Specified from -40℃ to +125℃\n? Packaging information: DIP16/SOP16/TSSOP16;

I-CORE

中微愛芯

2路JK觸發(fā)器，Dual JK Flip-Flop

CKS

中科芯

Dual J-K Master/Slave Flip-Flop with Set and Reset

General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edg

文件：68.79 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

Dual J-K Master/Slave Flip-Flop with Set and Reset

General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edg

文件：68.79 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

CMOS Dual J-K Master-Slave Flip-Flop

Description CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-out

文件：72.39 Kbytes 頁數(shù)：8 Pages

INTERSIL

CMOS Dual J-KMaster-Slave Flip-Flop

Features ? High Voltage Type (20V Rating) ? Set - Reset Capability ? Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low” ? Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V ? Standardized Symmetrical Output Characteristics ? 100 Test

文件：337.81 Kbytes 頁數(shù)：8 Pages

RENESAS

瑞薩