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          首頁(yè) >CD4015B>規(guī)格書(shū)列表

          型號(hào)下載 訂購(gòu)功能描述制造商 上傳企業(yè)LOGO

          CD4015B

          CMOS Dual 4-Stage Static Shift Register

          Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ? Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

          文件:686.94 Kbytes 頁(yè)數(shù):16 Pages

          TI

          德州儀器

          CD4015B

          CMOS Dual 4-Stage Static Shift Register

          Features: ? Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ? Fully static operation ? 8 master-slave flip-flops plus input and output buffering ? 100% tested for quiescent current at 20 V ?5.V, 10-V, and 15-V parametric ratings ? Standardized, symmetr

          文件:688.43 Kbytes 頁(yè)數(shù):16 Pages

          TI

          德州儀器

          CD4015B

          CMOS Dual 4-Stage Static Shift Register

          文件:521.58 Kbytes 頁(yè)數(shù):11 Pages

          TI

          德州儀器

          CD4015BC

          Dual 4-Bit Static Shift Register

          General Description The CD4015BC contains two identical, 4-stage, serial input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A

          文件:56.38 Kbytes 頁(yè)數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          CD4015BCM

          Dual 4-Bit Static Shift Register

          General Description The CD4015BC contains two identical, 4-stage, serial input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A

          文件:56.38 Kbytes 頁(yè)數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          CD4015BCN

          Dual 4-Bit Static Shift Register

          General Description The CD4015BC contains two identical, 4-stage, serial input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A

          文件:56.38 Kbytes 頁(yè)數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          CD4015BDTR

          CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

          Intersil’s Satellite Applications Flow? (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of r

          文件:74.24 Kbytes 頁(yè)數(shù):3 Pages

          INTERSIL

          CD4015BE

          絲印:CD4015BE;Package:PDIP;CMOS Dual 4-Stage Static Shift Register

          Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ? Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

          文件:686.94 Kbytes 頁(yè)數(shù):16 Pages

          TI

          德州儀器

          CD4015BE

          絲印:CD4015BE;Package:PDIP;CMOS Dual 4-Stage Static Shift Register

          Features: ? Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ? Fully static operation ? 8 master-slave flip-flops plus input and output buffering ? 100% tested for quiescent current at 20 V ?5.V, 10-V, and 15-V parametric ratings ? Standardized, symmetr

          文件:688.43 Kbytes 頁(yè)數(shù):16 Pages

          TI

          德州儀器

          CD4015BE.A

          CMOS Dual 4-Stage Static Shift Register

          Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ? Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

          文件:686.94 Kbytes 頁(yè)數(shù):16 Pages

          TI

          德州儀器

          技術(shù)參數(shù)

          • VCC(Min)(V):

            3

          • VCC(Max)(V):

            18

          • Voltage(Nom)(V):

            10

          • F @ nom voltage(Max)(MHz):

            8

          • ICC @ nom voltage(Max)(mA):

            0.3

          • tpd @ nom Voltage(Max)(ns):

            160

          • IOL(Max)(mA):

            1.5

          • IOH(Max)(mA):

            -1.5

          • 3-state output:

            No

          • Rating:

            Catalog

          • Operating temperature range(C):

            -55 to 125

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          NS
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          更多CD4015B供應(yīng)商 更新時(shí)間2026-1-18 8:01:00
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