Dual 4-Bit Static Shift Register

General Description The CD4015BC contains two identical, 4-stage, serial input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A

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FAIRCHILD

仙童半導(dǎo)體

Dual 4-Bit Static Shift Register

General Description The CD4015BC contains two identical, 4-stage, serial input/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A

文件：56.38 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導(dǎo)體

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Intersil’s Satellite Applications Flow? (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of r

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INTERSIL

CMOS Dual 4-Stage Static Shift Register

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TI

德州儀器