622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier

FEATURES Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV Independent slice level adjust and LOS detector No ref

文件：417.83 Kbytes 頁數(shù)：24 Pages

AD

亞德諾

622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier

GENERAL DESCRIPTION The ADN2804 provides the receiver functions of quantization, signal level detect, clock and data recovery, and data retiming for 622 Mbps NRZ data. The ADN2804 automatically locks to 622 Mbps data without the need for an external reference clock or programming. All SONET jitte

文件：460.77 Kbytes 頁數(shù)：24 Pages

AD

亞德諾

622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier

GENERAL DESCRIPTION The ADN2804 provides the receiver functions of quantization, signal level detect, clock and data recovery, and data retiming for 622 Mbps NRZ data. The ADN2804 automatically locks to 622 Mbps data without the need for an external reference clock or programming. All SONET jitte

文件：460.77 Kbytes 頁數(shù)：24 Pages

AD

亞德諾

622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier

FEATURES Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV Independent slice level adjust and LOS detector No ref

文件：417.83 Kbytes 頁數(shù)：24 Pages

AD

亞德諾

622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier

FEATURES Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV Independent slice level adjust and LOS detector No ref

文件：417.83 Kbytes 頁數(shù)：24 Pages

AD

亞德諾

622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier

GENERAL DESCRIPTION The ADN2804 provides the receiver functions of quantization, signal level detect, clock and data recovery, and data retiming for 622 Mbps NRZ data. The ADN2804 automatically locks to 622 Mbps data without the need for an external reference clock or programming. All SONET jitte

文件：460.77 Kbytes 頁數(shù)：24 Pages

AD

亞德諾

Package：32-WFQFN 裸露焊盤，CSP；包裝：卷帶（TR） 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC CLK/DATA REC 622MBPS 32-LFCSP

AD

亞德諾

Package：32-WFQFN 裸露焊盤，CSP；包裝：托盤 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC CLK/DATA REC 622MBPS 32-LFCSP

AD

亞德諾

Package：32-WFQFN 裸露焊盤，CSP；包裝：托盤 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC CLK/DATA REC 622MBPS 32-LFCSP

AD

亞德諾