OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

PRODUCT DESCRIPTION The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted

文件：359.97 Kbytes 頁數(shù)：16 Pages

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OC-48/OC-48 FEC Clock and Data Recovery

FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for both nati

文件：340.22 Kbytes 頁數(shù)：20 Pages

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OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

文件：485.78 Kbytes 頁數(shù)：20 Pages

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OC-48/OC-48 FEC時(shí)鐘和數(shù)據(jù)恢復(fù)

ADN2811可提供下列接收器功能：量化、信號(hào)電平檢測、時(shí)鐘和數(shù)據(jù)恢復(fù)，適用于OC-48和OC-48 FEC速率。該器件滿足所有的SONET抖動(dòng)要求，包括抖動(dòng)傳遞、抖動(dòng)產(chǎn)生和抖動(dòng)容差。所有規(guī)格均相對(duì)于-40℃至+85癈環(huán)境溫度而言，除非另有說明。\n\n 該器件主要用于WDM系統(tǒng)，可以結(jié)合外部參考時(shí)鐘或配有外部晶振的片內(nèi)振蕩器使用。ADN2811同時(shí)支持2.48 Gbps和2.66 Gbps數(shù)字包裝器速率，無需更改參考時(shí)鐘。\n\n 該器件配合PIN二極管和TIA前置放大器，可以實(shí)現(xiàn)高度集成的低成本、低功耗光纖接收器。\n\n 當(dāng)輸入信號(hào)電平降至用戶可調(diào)閾值以下時(shí) ? 符合SONET抖動(dòng)傳遞/產(chǎn)生/容差要求\n\n? 量化器靈敏度：4 mV（典型值）\n\n? 可調(diào)限幅電平：±100 mV\n\n? 帶寬：1.9 GHz（最小值）\n\n? 取得專利的時(shí)鐘恢復(fù)架構(gòu)\n\n? 信號(hào)丟失檢測范圍：3 mV至15 mV\n\n? 單一參考時(shí)鐘頻率同時(shí)適用于本有SONET和15/14 (7%)包裝器速率\n\n? 選擇19.44 MHz、38.88 MHz、77.76 MHz或155.52 MHz REFCLK\n\n? LVPECL/LVDS/LVCMOS/LVTTL兼容輸入（LVPECL/LVDS，僅在155.52 MHz時(shí)）\n\n? 19.44 ;

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OC-48/OC-48 FEC Clock and Data Recovery

FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for both nati

文件：340.22 Kbytes 頁數(shù)：20 Pages

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OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

PRODUCT DESCRIPTION The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted

文件：359.97 Kbytes 頁數(shù)：16 Pages

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OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

PRODUCT DESCRIPTION The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted

文件：359.97 Kbytes 頁數(shù)：16 Pages

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OC-48/OC-48 FEC Clock and Data Recovery

FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for both nati

文件：340.22 Kbytes 頁數(shù)：20 Pages

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OC-48/OC-48 FEC Clock and Data Recovery

FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for both nati

文件：340.22 Kbytes 頁數(shù)：20 Pages

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OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

文件：485.78 Kbytes 頁數(shù)：20 Pages

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