Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：478.05 Kbytes 頁數(shù)：28 Pages

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Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice

文件：409.25 Kbytes 頁數(shù)：28 Pages

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連續(xù)速率12.3 Mb/s至2.7 Gb/s時鐘和數(shù)據(jù)恢復(fù)IC，集成限幅放大器

ADN2812可提供下列接收器功能：量化、信號電平檢測、時鐘和數(shù)據(jù)恢復(fù)，適用于從12.3 Mb/s到2.7 Gb/s的連續(xù)數(shù)據(jù)速率。它可自動鎖定至所有數(shù)據(jù)速率，而無需外部參考時鐘或編程。該器件滿足所有的SONET抖動要求，包括抖動傳遞、抖動產(chǎn)生和抖動容差。所有規(guī)格均相對于?40°C至+85°C環(huán)境溫度而言，除非另有說明。 ?????????????????????????????????????\n\n 該器件配合PIN二極管和TIA前置放大器，可以實現(xiàn)高度集成的低成本、低功耗光纖接收器。\n\n 當(dāng)輸入信號電平降至用戶可調(diào)閾值以下時，接收器前端信號丟失(LOS)檢測電路會 ? 串行數(shù)據(jù)輸入：12.3 Mb/s至2.7 Gb/s\n\n? 超過SONET抖動傳遞/產(chǎn)生/容差要求\n\n? 量化器靈敏度：6 mV（典型值）\n\n? 可調(diào)限幅電平：±100 mV\n\n? 取得專利的時鐘恢復(fù)架構(gòu)\n\n? 信號丟失(LOS)檢測范圍：3 mV至15 mV\n\n? 獨立限幅電平調(diào)整和LOS檢測器\n\n? 無需參考時鐘\n\n? 失鎖指示器\n\n? 通過I2C 接口訪問可選特性\n\n? 單電源供電：3.3 V\n\n? 低功耗：750 mW（典型值）;

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亞德諾

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice

文件：409.25 Kbytes 頁數(shù)：28 Pages

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亞德諾

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：478.05 Kbytes 頁數(shù)：28 Pages

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亞德諾

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：478.05 Kbytes 頁數(shù)：28 Pages

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亞德諾

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：478.05 Kbytes 頁數(shù)：28 Pages

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亞德諾

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：409.83 Kbytes 頁數(shù)：28 Pages

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亞德諾

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice

文件：409.25 Kbytes 頁數(shù)：28 Pages

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亞德諾

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice

文件：409.25 Kbytes 頁數(shù)：28 Pages

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