155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2807 provides the receiver functions of quantization, signal level detect, and clock and data recovery at rates of OC-3, OC-12, and 15/14 FEC. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications a

文件：363.88 Kbytes 頁數(shù)：20 Pages

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155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amplifier

FEATURES Meets SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including 15/14 (7&#

文件：354.46 Kbytes 頁數(shù)：21 Pages

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155/622 Mbps時(shí)鐘和數(shù)據(jù)恢復(fù)IC，集成限幅放大器

ADN2807可提供下列接收器功能：量化、信號電平檢測、時(shí)鐘和數(shù)據(jù)恢復(fù)，適用于OC-3、OC-12和15/14 FEC數(shù)據(jù)速率。該器件滿足所有的SONET抖動(dòng)要求，包括抖動(dòng)傳遞、抖動(dòng)產(chǎn)生和抖動(dòng)容差。所有規(guī)格均相對于–40°C至+85°C環(huán)境溫度而言，除非另有說明。\n\n 該器件主要用于WDM系統(tǒng)，可以結(jié)合外部參考時(shí)鐘或配有外部晶振的片內(nèi)振蕩器使用。ADN2807同時(shí)支持本有速率和15/14速率數(shù)字包裝器，無需更改參考時(shí)鐘。\n\n 該器件配合PIN二極管和TIA前置放大器，可以實(shí)現(xiàn)高度集成的低成本、低功耗光纖接收器。\n\n 當(dāng)輸入信號電平降至用戶可調(diào)閾值以下時(shí) ? 符合SONET抖動(dòng)傳遞/產(chǎn)生/容差要求\n\n? 量化器靈敏度：4 mV（典型值）\n\n? 可調(diào)限幅電平：±100 mV\n\n? 取得專利的時(shí)鐘恢復(fù)架構(gòu)\n\n? 信號丟失檢測范圍：3 mV至15 mV\n\n? 單一參考時(shí)鐘頻率適用于所有速率，包括15/14 (7%)包裝器速率\n\n? 選擇19.44 MHz、38.88 MHz、77.76 MHz或155.52 MHz REFCLK\n\n? REFCLK輸入：LVPECL/LVDS/LVCMOS/LVTTL兼容（LVPECL/LVDS，僅在155.52 MHz時(shí)）\n\n? 可選19.44 MHz片內(nèi)振蕩器與外部晶振配合;

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155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amplifier

FEATURES Meets SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including 15/14 (7&#

文件：354.46 Kbytes 頁數(shù)：21 Pages

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155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2807 provides the receiver functions of quantization, signal level detect, and clock and data recovery at rates of OC-3, OC-12, and 15/14 FEC. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications a

文件：363.88 Kbytes 頁數(shù)：20 Pages

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亞德諾

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2807 provides the receiver functions of quantization, signal level detect, and clock and data recovery at rates of OC-3, OC-12, and 15/14 FEC. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications a

文件：363.88 Kbytes 頁數(shù)：20 Pages

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亞德諾

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amplifier

FEATURES Meets SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including 15/14 (7&#

文件：354.46 Kbytes 頁數(shù)：21 Pages

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155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amplifier

FEATURES Meets SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including 15/14 (7&#

文件：354.46 Kbytes 頁數(shù)：21 Pages

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155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

文件：534.21 Kbytes 頁數(shù)：20 Pages

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Package：48-WFQFN 裸露焊盤，CSP；包裝：散裝 類別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：IC CLOCK/DATA RECOVERY 48LFCSP

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