絲印：8541Y；Package：TQFP；16-BIT, SINGLE CHANNEL, PARALLEL INPUT DIGITAL-TO-ANALOG CONVERTER WITH RAIL-TO-RAIL VOLTAGE OUTPUT

FEATURES Micropower Operation: 250 μA at 5 V AVDD Power-On Reset to Min-Scale 16-Bit Monotonic Settling Time: 10 μs to ±0.003% FSR 16-Bit Parallel Interface On-Chip Output Buffer Amplifier With Rail-to-Rail Operation Hardware Reset to Min-Scale or Mid-Scale Double-Buffered Architectur

文件：626.22 Kbytes 頁數(shù)：25 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/8541y/marking.html">8541Y；Package：TQFP(PBS)；16-BIT, SINGLE CHANNEL, PARALLEL INPUT DIGITAL-TO-ANALOG CONVERTER WITH RAIL-TO-RAIL VOLTAGE OUTPUT

FEATURES Micropower Operation: 250 μA at 5 V AVDD Power-On Reset to Min-Scale 16-Bit Monotonic Settling Time: 10 μs to ±0.003% FSR 16-Bit Parallel Interface On-Chip Output Buffer Amplifier With Rail-to-Rail Operation Hardware Reset to Min-Scale or Mid-Scale Double-Buffered Architectur

文件：629.74 Kbytes 頁數(shù)：26 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/8541q/marking.html">8541Q；Package：VSSOP；SN74AC8541-Q1 Automotive Octal Buffers or Drivers With 3-State Outputs

1 Features ? AEC-Q100 qualified for automotive applications: – Device temperature grade 1: -40°C to +125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C4B ? Available in wettable flank QFN package ? Wide operating range of 1.5V to 6V ? Inputs accept voltage

文件：1.77336 Mbytes 頁數(shù)：30 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/8541c/marking.html">8541C；Package：SC70-5；OPERATION INSTRUCTION

文件：2.44234 Mbytes 頁數(shù)：21 Pages

COREBAI

芯佰微

M8 Connector Series | A | B | Coded

? M8 connector pin configurations: 3 pin, 4 pin, 5 pin, 6 pin, 8 pin\n? Meets IP66/IP67/IP68 water proof requirements\n? Available as loose piece or as pre-made M8 cables\n;

NorComp

Low Skew,1-to-4,Differential-to-LVDS Fanout Buffer

The 854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS), the 854104 provides a low power, low noise, solution for distributing ? Four differential LVDS output pairs\n? One differential clock input pair\n? CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n? Each output has an individual OE control\n? Maximum output frequency: 700MHz\n? Translates differential input signals to LVDS;

Renesas

瑞薩

Low Skew,1-to-4,LVCMOS/LVTTL-to-LVDS Fanout Buffer

The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100Ω. The 854105 accepts an LVCMOS/LVTTL i ·Four differential LVDS output pairs\n·One single-ended LVCMOS/LVTTL input\n·CLK can accept the following input levels: LVCMOS, LVTTL\n·Maximum output frequency: 250MHz\n·Translates single-ended input signals to LVDS levels\n·Additive phase jitter, RMS: 0.16ps (typical)\n·Output skew: 55ps (maximum);

Renesas

瑞薩

包裝：散裝 類別：標(biāo)簽，標(biāo)志，護(hù)欄，標(biāo)識 標(biāo)志，銘牌，招貼 描述：B302-10X14-YK-O-CAU-HAZARDOUS WA

Brady Corporation

包裝：散裝 類別：工具 壓接器，壓接機(jī)，壓力機(jī) - 配件 描述：STRIPPING ASSEMBLY

TE Application Tooling