包裝：散裝 類別：標(biāo)簽，標(biāo)志，護(hù)欄，標(biāo)識(shí) 標(biāo)志，銘牌，招貼 描述：B302-10X14-YK-O-CAU-HAZARDOUS WA

Brady Corporation

包裝：散裝 類別：標(biāo)簽，標(biāo)志，護(hù)欄，標(biāo)識(shí) 標(biāo)志，銘牌，招貼 描述：B302-10X14-YK-O-CAU-HAZARDOUS WA

Brady Corporation

M10X0.75 FEMALE THREAD DUST CAP W/ CHAIN

FEATURES M8 connector pin configurations: 3 pin, 4 pin, 5 pin, 6 pin Non-removable Contacts Meets IP67/IP68 water proof requirements -40°C to +85°C Temperature Range Available as loose piece or as pre-made M8 cables MATERIALS SHELL: Brass-Nickel Plated or Stainless Steel INSULATOR: PBT-B

文件：55.69 Kbytes 頁(yè)數(shù)：1 Pages

NORCOMP

Low Skew, 1-to-4, LVCMOS/LVTTL-to-LVDS Fanout Buffer

General Description The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100?. The 85410

文件：407.49 Kbytes 頁(yè)數(shù)：14 Pages

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Low Skew, 1-to-4, LVCMOS/ LVTTL-to-LVDS Fanout Buffer

General Description The 854105I is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105I provides a low power, low noise solution for distributing clock signals over controlled impedances of 100?. The 854

文件：474.56 Kbytes 頁(yè)數(shù)：14 Pages

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絲?。?a target="_blank" title="Marking" href="/54104ail/marking.html">54104AIL；Package：TSSOP；Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

文件：321.31 Kbytes 頁(yè)數(shù)：15 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/54104ail/marking.html">54104AIL；Package：TSSOP；Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

文件：321.31 Kbytes 頁(yè)數(shù)：15 Pages

IDT

M8 Connector Series | A | B | Coded

? M8 connector pin configurations: 3 pin, 4 pin, 5 pin, 6 pin, 8 pin\n? Meets IP66/IP67/IP68 water proof requirements\n? Available as loose piece or as pre-made M8 cables\n;

NorComp

Low Skew,1-to-4,Differential-to-LVDS Fanout Buffer

The 854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS), the 854104 provides a low power, low noise, solution for distributing ? Four differential LVDS output pairs\n? One differential clock input pair\n? CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n? Each output has an individual OE control\n? Maximum output frequency: 700MHz\n? Translates differential input signals to LVDS;

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Low Skew,1-to-4,LVCMOS/LVTTL-to-LVDS Fanout Buffer

The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100Ω. The 854105 accepts an LVCMOS/LVTTL i ·Four differential LVDS output pairs\n·One single-ended LVCMOS/LVTTL input\n·CLK can accept the following input levels: LVCMOS, LVTTL\n·Maximum output frequency: 250MHz\n·Translates single-ended input signals to LVDS levels\n·Additive phase jitter, RMS: 0.16ps (typical)\n·Output skew: 55ps (maximum);

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