T-1 Subminiature Lamps

T-1? Subminiature Lamps

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GILWAY

INDUCTORS Inductors Designed for Nationals 150 KHz SIMPLE SWITCHERTM

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FILTRAN

費(fèi)爾蘭特

AXL E EC DI16 M12 6P

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PHOENIXPHOENIX CONTACT

菲尼克斯德國(guó)菲尼克斯電氣集團(tuán)

絲?。?strong>8541；Package：VSSOP；SN74AC8541 Octal Buffers or Drivers With 3-State Outputs

1 Features ? Wide operating range of 1.5V to 6V ? Inputs accept voltages up to 6V ? Continuous ±24mA output drive at 5V ? Supports up to ±75mA output drive at 5V in short bursts ? Drives 50Ω transmission lines ? Maximum tpd of 6ns at 5V, 50pF load 2 Applications ? Enable or disable a di

文件：1.71108 Mbytes 頁(yè)數(shù)：28 Pages

TI

德州儀器

絲印：8541；Package：SOT23-5；OPERATION INSTRUCTION

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COREBAI

芯佰微

包裝：散裝 類別：五金件，緊固件，配件 旋鈕 描述：KNOB KNURLED 0.125\

Keystone Electronics

M10X0.75 FEMALE THREAD DUST CAP W/ CHAIN

FEATURES M8 connector pin configurations: 3 pin, 4 pin, 5 pin, 6 pin Non-removable Contacts Meets IP67/IP68 water proof requirements -40°C to +85°C Temperature Range Available as loose piece or as pre-made M8 cables MATERIALS SHELL: Brass-Nickel Plated or Stainless Steel INSULATOR: PBT-B

文件：55.69 Kbytes 頁(yè)數(shù)：1 Pages

NORCOMP

Low Skew, 1-to-4, LVCMOS/LVTTL-to-LVDS Fanout Buffer

General Description The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100?. The 85410

文件：407.49 Kbytes 頁(yè)數(shù)：14 Pages

RENESAS

瑞薩

Low Skew, 1-to-4, LVCMOS/ LVTTL-to-LVDS Fanout Buffer

General Description The 854105I is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105I provides a low power, low noise solution for distributing clock signals over controlled impedances of 100?. The 854

文件：474.56 Kbytes 頁(yè)數(shù)：14 Pages

RENESAS

瑞薩

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES ? Two differential LVDS outputs ? One differential CLK, nCLK clock input ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Maximum output frequency: 650MHz ? Translates any single ended input signal to LVDS levels with resistor

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RENESAS

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