Triple 3-Input NAND Gate

General Description This device contains three independent gates each of which performs the logic NAND function.

文件：93.46 Kbytes 頁(yè)數(shù)：4 Pages

SYC

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Depondable Texas Instruments Quality and Reliability

文件：409.11 Kbytes 頁(yè)數(shù)：12 Pages

TI

德州儀器

LOW POWER SCHOTTKY

LOW POWER SCHOTTKY The SN74LS109A consists of two high speed completely independent transition clocked JKflip-flops.

文件：96.07 Kbytes 頁(yè)數(shù)：4 Pages

ONSEMI

安森美半導(dǎo)體

Triple 3-Input AND Gate

General Description This device contains three independent gates each of which performs the logic AND function. Features ■ Alternate military/aerospace device (54LS11) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.

文件：46.02 Kbytes 頁(yè)數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

Triple 3-Input AND Gate

General Description This device contains three independent gates each of which performs the logic AND function.

文件：93.18 Kbytes 頁(yè)數(shù)：4 Pages

SYC

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

文件：56.62 Kbytes 頁(yè)數(shù)：1 Pages

ETCList of Unclassifed Manufacturers

未分類制造商

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

文件：147.33 Kbytes 頁(yè)數(shù)：4 Pages

MOTOROLA

摩托羅拉

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：52 Kbytes 頁(yè)數(shù)：5 Pages

FAIRCHILD

仙童半導(dǎo)體

Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)

文件：76.76 Kbytes 頁(yè)數(shù)：7 Pages

HITACHIHitachi Semiconductor

日立日立公司

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：52 Kbytes 頁(yè)數(shù)：5 Pages

FAIRCHILD

仙童半導(dǎo)體