Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：52 Kbytes 頁數(shù)：5 Pages

FAIRCHILD

仙童半導(dǎo)體

Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)

文件：76.76 Kbytes 頁數(shù)：7 Pages

HITACHIHitachi Semiconductor

日立日立公司

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

文件：147.33 Kbytes 頁數(shù)：4 Pages

MOTOROLA

摩托羅拉

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件：300.4 Kbytes 頁數(shù)：9 Pages

TI

德州儀器

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

ONSEMI

安森美半導(dǎo)體

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：52 Kbytes 頁數(shù)：5 Pages

FAIRCHILD

仙童半導(dǎo)體

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

文件：147.21 Kbytes 頁數(shù)：4 Pages

MOTOROLA

摩托羅拉