絲?。?strong>74HC132；Package：S014；Quad 2-input Schmitt NAND gate

Features ? High-speed: tPD = 11 ns (typ.) at VCC = 6 V ? Low power dissipation: ICC = 1 μA (max.) at TA = 25 °C ? High noise immunity: VH(typ) = 0.9 V at VCC = 5 V ? Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) ? Balanced propagation delays: tPLH ? tPHL ? Wide operating volta

文件：477.03 Kbytes 頁數(shù)：13 Pages

STMICROELECTRONICS

意法半導(dǎo)體

絲?。?a target="_blank" title="Marking" href="/74hc132d/marking.html">74HC132D；Package：SOIC14；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? Quad 2-Input Schmitt NAND Gate General The 74HC132D is a high speed CMOS 2-INPUT NAND SCHMITT TRIGGER GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation

文件：177.99 Kbytes 頁數(shù)：8 Pages

TOSHIBA

東芝

絲?。?a target="_blank" title="Marking" href="/74hc132y/marking.html">74HC132Y；Package：SO14(automotivegrade)；Quad 2-input Schmitt NAND gate

Features ? High-speed: tPD = 11 ns (typ.) at VCC = 6 V ? Low power dissipation: ICC = 1 μA (max.) at TA = 25 °C ? High noise immunity: VH(typ) = 0.9 V at VCC = 5 V ? Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) ? Balanced propagation delays: tPLH ? tPHL ? Wide operating volta

文件：477.03 Kbytes 頁數(shù)：13 Pages

STMICROELECTRONICS

意法半導(dǎo)體

絲?。?a target="_blank" title="Marking" href="/74hc132d/marking.html">74HC132D；Package：SOIC14；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? Quad 2-Input Schmitt NAND Gate General The 74HC132D is a high speed CMOS 2-INPUT NAND SCHMITT TRIGGER GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation

文件：177.99 Kbytes 頁數(shù)：8 Pages

TOSHIBA

東芝

Quad 2-input NAND Schmitt trigger

1. General description The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals

文件：269.66 Kbytes 頁數(shù)：16 Pages

NEXPERIA

安世

High Speed CMOS Logic

Features High Speed: tPD = 11ns @ 5V (Typ.) Low Input Current: 1μA Output Drive Capability: 10 LSTTL loads Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS132.

文件：269.57 Kbytes 頁數(shù)：5 Pages

SS

Quad 2-input NAND Schmitt trigger

GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable

文件：70.63 Kbytes 頁數(shù)：8 Pages

PHI

PHI

Quad 2??nput NAND Gate with Schmitt??rigger Inputs High??erformance Silicon??ate CMOS

Quad 2?Input NAND Gate with Schmitt?Trigger Inputs High?Performance Silicon?Gate CMOS The 74HC132 is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull?up resistors, they are compatible with LSTTL outputs. The HC132 can be used to enhance no

文件：140.39 Kbytes 頁數(shù)：9 Pages

ONSEMI

安森美半導(dǎo)體

High Speed CMOS Logic

Features High Speed: tPD = 11ns @ 5V (Typ.) Low Input Current: 1μA Output Drive Capability: 10 LSTTL loads Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS132.

文件：269.57 Kbytes 頁數(shù)：5 Pages

SS

Quad 2-input NAND Schmitt trigger

1. General description The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals

文件：269.66 Kbytes 頁數(shù)：16 Pages

NEXPERIA

安世