絲印：74HC138D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? 3-to-8 Line Decoder General The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled,

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TOSHIBA

東芝

絲?。?strong>74HC138D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description ? 3-to-8 Line Decoder General The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled,

文件：212.38 Kbytes 頁(yè)數(shù)：9 Pages

TOSHIBA

東芝

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Demultiplexing capability ? Multiple input enable for easy expansion ? Ideal for memory

文件：50.49 Kbytes 頁(yè)數(shù)：7 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features and benefits ■ Demultiplexing capability ■ Multiple input enable for easy expansion ■ Complies with JEDEC standard no. 7A ■ Ideal for memory chi

文件：211.62 Kbytes 頁(yè)數(shù)：19 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple ena

文件：274.63 Kbytes 頁(yè)數(shù)：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

General description The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features and benefits ■ Demultiplexing capability ■ Multiple input enable for easy expansion ■ Complies with JEDEC standard no. 7A ■ Ideal for memory chi

文件：211.62 Kbytes 頁(yè)數(shù)：19 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Demultiplexing capability ? Multiple input enable for easy expansion ? Ideal for memory

文件：50.49 Kbytes 頁(yè)數(shù)：7 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This m

文件：273.19 Kbytes 頁(yè)數(shù)：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

General description The 74HC138-Q100; 74HCT138-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Grade 1) ◆ Specified from -40 °C to +85 °C and from -40 °

文件：241.85 Kbytes 頁(yè)數(shù)：18 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

文件：211.62 Kbytes 頁(yè)數(shù)：19 Pages

恩XP