<strong id="5lvfi"><dl id="5lvfi"></dl></strong>

      • <tfoot id="5lvfi"><menuitem id="5lvfi"></menuitem></tfoot>
        <th id="5lvfi"><progress id="5lvfi"></progress></th>
          <strong id="5lvfi"><form id="5lvfi"></form></strong>
          <strong id="5lvfi"><form id="5lvfi"></form></strong>
        1. <del id="5lvfi"></del>
          型號下載 訂購功能描述制造商 上傳企業(yè)LOGO

          SN74F112NSR

          絲印:74F112;Package:SOP;DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

          Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

          文件:566.64 Kbytes 頁數(shù):16 Pages

          TI

          德州儀器

          SN74F112NSR.A

          絲?。?strong>74F112;Package:SOP;DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

          Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

          文件:566.64 Kbytes 頁數(shù):16 Pages

          TI

          德州儀器

          74F112

          Dual JK Negative Edge-Triggered Flip-Flop

          General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

          文件:59.07 Kbytes 頁數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          74F112

          Dual J-K negative edge-triggered flip-flop

          DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

          文件:83.94 Kbytes 頁數(shù):10 Pages

          PHI

          PHI

          PHI

          74F112PC

          Dual JK Negative Edge-Triggered Flip-Flop

          General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

          文件:59.07 Kbytes 頁數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          74F112SC

          Dual JK Negative Edge-Triggered Flip-Flop

          General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

          文件:59.07 Kbytes 頁數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          74F112SJ

          Dual JK Negative Edge-Triggered Flip-Flop

          General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

          文件:59.07 Kbytes 頁數(shù):6 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          74F112

          Dual JK Negative Edge-Triggered Flip-Flop

          文件:83.34 Kbytes 頁數(shù):7 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          74F112_00

          Dual JK Negative Edge-Triggered Flip-Flop

          文件:83.34 Kbytes 頁數(shù):7 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          74F112PC

          Dual JK Negative Edge-Triggered Flip-Flop

          文件:83.34 Kbytes 頁數(shù):7 Pages

          FAIRCHILD

          仙童半導(dǎo)體

          詳細(xì)參數(shù)

          • 型號:

            74F112

          • 功能描述:

            觸發(fā)器 Dual Neg-Edge-Trig J-K Flip-Flop

          • RoHS:

          • 制造商:

            Texas Instruments

          • 電路數(shù)量:

            2

          • 邏輯系列:

            SN74

          • 邏輯類型:

            D-Type Flip-Flop

          • 極性:

            Inverting, Non-Inverting

          • 輸入類型:

            CMOS

          • 傳播延遲時間:

            4.4 ns

          • 高電平輸出電流:

            - 16 mA

          • 低電平輸出電流:

            16 mA

          • 電源電壓-最大:

            5.5 V

          • 最大工作溫度:

            + 85 C

          • 安裝風(fēng)格:

            SMD/SMT

          • 封裝/箱體:

            X2SON-8

          • 封裝:

            Reel

          供應(yīng)商型號品牌批號封裝庫存備注價格
          TI
          24+
          SMD
          3000
          自己現(xiàn)貨
          詢價
          Texas Instruments
          24+
          16-SOIC(0.209
          56300
          詢價
          TI
          25+
          IC
          9854
          就找我吧!--邀您體驗愉快問購元件!
          詢價
          22+
          NA
          3450
          加我QQ或微信咨詢更多詳細(xì)信息,
          詢價
          TI/德州儀器
          23+
          SOP16-5.2
          50000
          全新原裝正品現(xiàn)貨,支持訂貨
          詢價
          TI
          22+
          16SOIC
          9000
          原廠渠道,現(xiàn)貨配單
          詢價
          TI/德州儀器
          23+
          SOP
          3200
          正規(guī)渠道,只有原裝!
          詢價
          TI
          SOP-0.52
          68500
          一級代理 原裝正品假一罰十價格優(yōu)勢長期供貨
          詢價
          TI/德州儀器
          25+
          SOP-16
          30000
          公司只有原裝
          詢價
          TI
          23+
          SO-16
          62523
          公司原裝現(xiàn)貨!主營品牌!可含稅歡迎查詢
          詢價
          更多74F112供應(yīng)商 更新時間2026-1-18 16:00:00
            <strong id="5lvfi"><dl id="5lvfi"></dl></strong>

              • <tfoot id="5lvfi"><menuitem id="5lvfi"></menuitem></tfoot>
                <th id="5lvfi"><progress id="5lvfi"></progress></th>
                  <strong id="5lvfi"><form id="5lvfi"></form></strong>
                  <strong id="5lvfi"><form id="5lvfi"></form></strong>
                1. <del id="5lvfi"></del>
                  亚洲怡春院 | 亚洲vo1 | 2019国产在线自内拍视频 | 在线国产播放 | 黄色片网站视频看免费在线 |