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          首頁 >PLL1>規(guī)格書列表

          型號下載 訂購功能描述制造商 上傳企業(yè)LOGO

          PLL103-05SC

          1-to-5 Clock Distribution Buffer

          DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES ? 5 outputs identical to FIN. ? Low skew (

          文件:122.15 Kbytes 頁數(shù):4 Pages

          PLL

          PLL103-05SI

          1-to-5 Clock Distribution Buffer

          DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES ? 5 outputs identical to FIN. ? Low skew (

          文件:122.15 Kbytes 頁數(shù):4 Pages

          PLL

          PLL103-05SM

          1-to-5 Clock Distribution Buffer

          DESCRIPTIONS The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. FEATURES ? 5 outputs identical to FIN. ? Low skew (

          文件:122.15 Kbytes 頁數(shù):4 Pages

          PLL

          PLL103-06

          DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

          DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with

          文件:145.87 Kbytes 頁數(shù):7 Pages

          PLL

          PLL103-06XC

          DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

          DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with

          文件:145.87 Kbytes 頁數(shù):7 Pages

          PLL

          PLL103-06XI

          DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

          DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with

          文件:145.87 Kbytes 頁數(shù):7 Pages

          PLL

          PLL103-06XM

          DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

          DESCRIPTIONS The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with

          文件:145.87 Kbytes 頁數(shù):7 Pages

          PLL

          PLL103-07

          2 DIMM DDR Fanout Buffer

          DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2

          文件:144.26 Kbytes 頁數(shù):7 Pages

          PLL

          PLL103-07XC

          2 DIMM DDR Fanout Buffer

          DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2

          文件:144.26 Kbytes 頁數(shù):7 Pages

          PLL

          PLL103-07XI

          2 DIMM DDR Fanout Buffer

          DESCRIPTIONS The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 2

          文件:144.26 Kbytes 頁數(shù):7 Pages

          PLL

          產(chǎn)品屬性

          • 產(chǎn)品編號:

            PLL1

          • 制造商:

            Altech Corporation

          • 類別:

            光電器件 > 配件

          • 包裝:

            散裝

          • 描述:

            LENSPILOT LIGHT 30 MM WHITE

          供應(yīng)商型號品牌批號封裝庫存備注價(jià)格
          24+
          N/A
          65000
          一級代理-主營優(yōu)勢-實(shí)惠價(jià)格-不悔選擇
          詢價(jià)
          BB
          05+
          SSOP20
          4600
          全新原裝進(jìn)口自己庫存優(yōu)勢
          詢價(jià)
          BB
          SSOP
          6
          詢價(jià)
          TI&BB
          17+
          QSOP20
          6200
          100%原裝正品現(xiàn)貨
          詢價(jià)
          BB
          23+
          SSOP-20
          5700
          絕對全新原裝!現(xiàn)貨!特價(jià)!請放心訂購!
          詢價(jià)
          BB
          25+
          SSOP-20
          2500
          強(qiáng)調(diào)現(xiàn)貨,隨時(shí)查詢!
          詢價(jià)
          TI
          24+
          26
          詢價(jià)
          TI
          05+
          原廠原裝
          2051
          只做全新原裝真實(shí)現(xiàn)貨供應(yīng)
          詢價(jià)
          BB
          25+
          DIP
          18000
          原廠直接發(fā)貨進(jìn)口原裝
          詢價(jià)
          TI
          2016+
          QSOP20
          3500
          只做原裝,假一罰十,公司可開17%增值稅發(fā)票!
          詢價(jià)
          更多PLL1供應(yīng)商 更新時(shí)間2026-1-20 11:06:00
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