Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

文件：166.6 Kbytes 頁數(shù)：10 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

文件：180.37 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

文件：180.37 Kbytes 頁數(shù)：6 Pages

PLL

Low Skew Output Buffer

DESCRIPTIONS The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to t

文件：109.93 Kbytes 頁數(shù)：8 Pages

PLL

Low Skew Output Buffer

DESCRIPTIONS The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to t

文件：109.93 Kbytes 頁數(shù)：8 Pages

PLL

Low Skew Buffers

FEATURES ? Generate 18 copies of High-speed clock inputs. ? Supports up to four SDRAM DIMMS synchronous clocks. ? Supports 2-wire I2C serial bus interface with readback. ? 50 duty cycle with low jitter. ? Less than 5ns delay. ? Skew between any outputs is less than 250 ps. ? Tri-state pin f

文件：69.7 Kbytes 頁數(shù)：7 Pages

PLL

Low Skew Buffers

FEATURES ? Generate 18 copies of High-speed clock inputs. ? Supports up to four SDRAM DIMMS synchronous clocks. ? Supports 2-wire I2C serial bus interface with readback. ? 50 duty cycle with low jitter. ? Less than 5ns delay. ? Skew between any outputs is less than 250 ps. ? Tri-state pin f

文件：69.7 Kbytes 頁數(shù)：7 Pages

PLL

Low Skew Buffers

FEATURES ? Generate 18 copies of High-speed clock inputs. ? Supports up to four SDRAM DIMMS synchronous clocks. ? Supports 2-wire I2C serial bus interface with readback. ? 50 duty cycle with low jitter. ? Less than 5ns delay. ? Skew between any outputs is less than 250 ps. ? Tri-state pin f

文件：69.7 Kbytes 頁數(shù)：7 Pages

PLL

Low Skew Buffers

FEATURES ? Generate 18 copies of High-speed clock inputs. ? Supports up to four SDRAM DIMMS synchronous clocks. ? Supports 2-wire I2C serial bus interface with readback. ? 50 duty cycle with low jitter. ? Less than 5ns delay. ? Skew between any outputs is less than 250 ps. ? Tri-state pin f

文件：69.7 Kbytes 頁數(shù)：7 Pages

PLL

DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

[PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02

文件：208.36 Kbytes 頁數(shù)：7 Pages

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