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首頁(yè) >PCK>規(guī)格書列表

型號(hào)	下載訂購(gòu)	功能描述	制造商上傳企業(yè)	LOGO
PCK2509SA	文件：79.02 Kbytes Page：10 Pages	50-150 MHz 1:9 SDRAM clock driver DESCRIPTION The PCK2509SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The 文件：79.02 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2509SADH	文件：79.02 Kbytes Page：10 Pages	50-150 MHz 1:9 SDRAM clock driver DESCRIPTION The PCK2509SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The 文件：79.02 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2509SL	文件：79.61 Kbytes Page：10 Pages	50-150 MHz 1:9 SDRAM clock driver DESCRIPTION The PCK2509SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The 文件：79.61 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2509SLDH	文件：79.61 Kbytes Page：10 Pages	50-150 MHz 1:9 SDRAM clock driver DESCRIPTION The PCK2509SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The 文件：79.61 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2509SPW	文件：70.65 Kbytes Page：10 Pages	50-150 MHz 1:9 SDRAM clock driver DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PC 文件：70.65 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2510S	文件：81.51 Kbytes Page：10 Pages	50-150 MHz 1:10 SDRAM clock driver DESCRIPTION The PCK2510S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The P 文件：81.51 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2510SA	文件：78.22 Kbytes Page：10 Pages	50-150 MHz 1:10 SDRAM clock driver DESCRIPTION The PCK2510SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The 文件：78.22 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2510SADH	文件：78.22 Kbytes Page：10 Pages	50-150 MHz 1:10 SDRAM clock driver DESCRIPTION The PCK2510SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The 文件：78.22 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2510SL	文件：78.53 Kbytes Page：10 Pages	50-150 MHz 1:10 SDRAM clock driver DESCRIPTION The PCK2510SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The 文件：78.53 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI
PCK2510SLDH	文件：78.53 Kbytes Page：10 Pages	50-150 MHz 1:10 SDRAM clock driver DESCRIPTION The PCK2510SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The 文件：78.53 Kbytes 頁(yè)數(shù)：10 Pages	PHI PHI	PHI

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技術(shù)參數(shù)

額定電壓[Vdc]：
2.5
額定靜電容量[μF]：
1
額定靜電容量容許差[%]：
-20～20
產(chǎn)品直徑： D[㎜]：
10.0
產(chǎn)品高度： L[㎜]：
8.0
類別下限溫度[℃]：
-55
類別上限溫度[℃]：
105
耐久性[h]：
2
參考重量[g]：
0.85
損耗角正切（tanδ）：
0.12
漏電流[μA]：
900
額定紋波電流1(mArms)：
5
ESR(mΩ)（20℃/100kHz）：
9
最小包裝單位：
500
品種：
芯片類型
產(chǎn)品概要：
超低ESR產(chǎn)品
有無極性：
極性
耐振動(dòng)對(duì)應(yīng)品：
不兼容的產(chǎn)品
低溫ESR規(guī)定品：
非標(biāo)產(chǎn)品
符合AEC-Q200：
合規(guī)產(chǎn)品
音響品：
不兼容的產(chǎn)品

供應(yīng)商	型號(hào)	品牌	批號(hào)	封裝	庫(kù)存	備注	價(jià)格
深圳龐田科技有限公司	PCK	OEG	2023+環(huán)?，F(xiàn)貨	專業(yè)繼電器	6800	專注軍工、汽車、醫(yī)療、工業(yè)等方案配套一站式服務(wù)	詢價(jià)
深圳市益百分電子有限公司	PCK953BD	PHI	02+	QFP32	1200	全新原裝進(jìn)口自己庫(kù)存優(yōu)勢(shì)	詢價(jià)
深圳市勤思達(dá)科技有限公司	PCK2057DGG	恩XP	09+	TSSOP	5500	原裝無鉛,優(yōu)勢(shì)熱賣	詢價(jià)
深圳市聯(lián)世界科技有限公司	PCK111A	PHIL	24+/25+		17	原裝正品現(xiàn)貨庫(kù)存價(jià)優(yōu)	詢價(jià)
諦輝(北京/上海/青島 )電子科技有限公司	PCK2057DGG	PHI	25+	TSSOP	18000	原廠直接發(fā)貨進(jìn)口原裝	詢價(jià)
深圳市福安甌科技有限公司	PCK2510SA	PHI	25+	TSSOP24	1745	⊙⊙新加坡大量現(xiàn)貨庫(kù)存,深圳常備現(xiàn)貨!歡迎查詢!⊙	詢價(jià)
芯有半導(dǎo)體（深圳）有限公司	PCK2008	PHI	00+	SOP48	49	全新原裝100真實(shí)現(xiàn)貨供應(yīng)	詢價(jià)
深圳市毅創(chuàng)騰電子科技有限公司	PCK857DGG	PHI	23+	TSSOP/48	7000	絕對(duì)全新原裝!100%保質(zhì)量特價(jià)!請(qǐng)放心訂購(gòu)!	詢價(jià)
深圳市卓越微芯電子有限公司	PCK2002PLPW	恩XP	25+	MSOP8	75	百分百原裝正品真實(shí)公司現(xiàn)貨庫(kù)存本公司只做原裝可	詢價(jià)
深圳市恒創(chuàng)達(dá)實(shí)業(yè)有限公司	PCKI	TI	17+	SOT-153	6200	100%原裝正品現(xiàn)貨	詢價(jià)

更多PCK供應(yīng)商更新時(shí)間2024-3-26 15:06:00

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