| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
CK00 100/133 MHz spread spectrum differential system clock generator DESCRIPTION The PCK2022R is a clock synthesizer/driver for a Pentium III? and other similar processors The PCK2022R has eight differential pair CPU current source outputs, one 33/66 MHz output which is configurable on power-up, two 48 MHz clocks which can be disabled on power-up, and one 3.3 V r 文件：102.32 Kbytes 頁數(shù)：14 Pages | PHI PHI | PHI | ||
CK408 66/100/133/200 MHz spread spectrum differential system clock generator DESCRIPTION The PCK2023 is a clock synthesizer/driver for a Pentium IV and other similar processors. The PCK2023 has three differential pair CPU current source outputs. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. There are six 3V66 outputs. Finally, there is one 3.3 文件：177.86 Kbytes 頁數(shù)：30 Pages | PHI PHI | PHI | ||
CK408 66/100/133/200 MHz spread spectrum differential system clock generator DESCRIPTION The PCK2023 is a clock synthesizer/driver for a Pentium IV and other similar processors. The PCK2023 has three differential pair CPU current source outputs. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. There are six 3V66 outputs. Finally, there is one 3.3 文件：177.86 Kbytes 頁數(shù)：30 Pages | PHI PHI | PHI | ||
CK408 66/100/133/200 MHz spread spectrum differential system clock generator DESCRIPTION The PCK2023 is a clock synthesizer/driver for a Pentium IV and other similar processors. The PCK2023 has three differential pair CPU current source outputs. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. There are six 3V66 outputs. Finally, there is one 3.3 文件：177.86 Kbytes 頁數(shù)：30 Pages | PHI PHI | PHI | ||
70 - 190 MHz I2C differential 1:10 clock driver DESCRIPTION The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (C 文件：95.18 Kbytes 頁數(shù)：12 Pages | PHI PHI | PHI | ||
70 - 190 MHz I2C differential 1:10 clock driver DESCRIPTION The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (C 文件：95.18 Kbytes 頁數(shù)：12 Pages | PHI PHI | PHI | ||
Low voltage dual 1-5 differential ECL/PECL clock driver DESCRIPTION The PCK210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The input signals can be either differential or single-ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. The PCK210 is specifically designe 文件：93.44 Kbytes 頁數(shù)：10 Pages | PHI PHI | PHI | ||
Low voltage dual 1-5 differential ECL/PECL clock driver DESCRIPTION The PCK210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The input signals can be either differential or single-ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. The PCK210 is specifically designe 文件：93.44 Kbytes 頁數(shù)：10 Pages | PHI PHI | PHI | ||
Low voltage dual 1-5 differential ECL/PECL clock driver DESCRIPTION The PCK210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The input signals can be either differential or single-ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. The PCK210 is specifically designe 文件：93.44 Kbytes 頁數(shù)：10 Pages | PHI PHI | PHI | ||
50-150 MHz 1:9 SDRAM clock driver DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PC 文件：70.65 Kbytes 頁數(shù)：10 Pages | PHI PHI | PHI |
技術(shù)參數(shù)
- 額定電壓[Vdc]：
2.5
- 額定靜電容量[μF]：
1
- 額定靜電容量容許差[%]：
-20～20
- 產(chǎn)品直徑： D[㎜]：
10.0
- 產(chǎn)品高度： L[㎜]：
8.0
- 類別下限溫度[℃]：
-55
- 類別上限溫度[℃]：
105
- 耐久性[h]：
2
- 參考重量[g]：
0.85
- 損耗角正切（tanδ）：
0.12
- 漏電流[μA]：
900
- 額定紋波電流1(mArms)：
5
- ESR(mΩ)（20℃/100kHz）：
9
- 最小包裝單位：
500
- 品種：
芯片類型
- 產(chǎn)品概要：
超低ESR產(chǎn)品
- 有無極性：
極性
- 耐振動對應(yīng)品：
不兼容的產(chǎn)品
- 低溫ESR規(guī)定品：
非標(biāo)產(chǎn)品
- 符合AEC-Q200：
合規(guī)產(chǎn)品
- 音響品：
不兼容的產(chǎn)品
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
OEG |
2023+環(huán)?，F(xiàn)貨 |
專業(yè)繼電器 |
6800 |
專注軍工、汽車、醫(yī)療、工業(yè)等方案配套一站式服務(wù) |
詢價(jià) | ||
PHI |
02+ |
QFP32 |
1200 |
全新原裝進(jìn)口自己庫存優(yōu)勢 |
詢價(jià) | ||
恩XP |
09+ |
TSSOP |
5500 |
原裝無鉛,優(yōu)勢熱賣 |
詢價(jià) | ||
PHIL |
24+/25+ |
17 |
原裝正品現(xiàn)貨庫存價(jià)優(yōu) |
詢價(jià) | |||
PHI |
25+ |
TSSOP |
18000 |
原廠直接發(fā)貨進(jìn)口原裝 |
詢價(jià) | ||
PHI |
25+ |
TSSOP24 |
1745 |
⊙⊙新加坡大量現(xiàn)貨庫存,深圳常備現(xiàn)貨!歡迎查詢!⊙ |
詢價(jià) | ||
PHI |
00+ |
SOP48 |
49 |
全新原裝100真實(shí)現(xiàn)貨供應(yīng) |
詢價(jià) | ||
PHI |
23+ |
TSSOP/48 |
7000 |
絕對全新原裝!100%保質(zhì)量特價(jià)!請放心訂購! |
詢價(jià) | ||
恩XP |
25+ |
MSOP8 |
75 |
百分百原裝正品 真實(shí)公司現(xiàn)貨庫存 本公司只做原裝 可 |
詢價(jià) | ||
TI |
17+ |
SOT-153 |
6200 |
100%原裝正品現(xiàn)貨 |
詢價(jià) |
相關(guān)規(guī)格書
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- SI7970DP
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- SPC5605BF1MLQ6
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- XRCGB25M000F3N00R0
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- PS9352AL2
- PS9306L
- PS9307L
- PS9303L2
- PS9331L2
- PS9309L
- PS9324L2
- PS9309L
