Communications Clock PLLs

Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation

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Communications Clock PLLs

Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation

文件：148.24 Kbytes 頁數(shù)：12 Pages

ICST

Communications Clock PLLs

Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation

文件：148.24 Kbytes 頁數(shù)：12 Pages

ICST

3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features ? Packaged in 20-pin SOIC ? 3.3 V + 5 operation ? Fixed I/O phase relationship on all selections ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8

文件：256.38 Kbytes 頁數(shù)：10 Pages

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3.3 V Communications Clock PLL

Description The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks freq

文件：135.66 Kbytes 頁數(shù)：11 Pages

ICST

3.3 Volt Communications Clock VCXO PLL

Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clo

文件：136.47 Kbytes 頁數(shù)：8 Pages

ICST

3.3 Volt Communications Clock VCXO PLL

Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clo

文件：136.47 Kbytes 頁數(shù)：8 Pages

ICST

3.3 Volt Communications Clock VCXO PLL

Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clo

文件：136.47 Kbytes 頁數(shù)：8 Pages

ICST

絲?。?a target="_blank" title="Marking" href="/mk2049-34si/marking.html">MK2049-34SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features ? Packaged in 20-pin SOIC ? 3.3 V + 5 operation ? Fixed I/O phase relationship on all selections ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8

文件：256.38 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩

3.3 V Communications Clock PLL

Description The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks freq

文件：135.66 Kbytes 頁數(shù)：11 Pages

ICST