絲印：MK2049-36SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20 pin SOIC ? Pb (lead) free package ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock or

文件：248.79 Kbytes 頁數(shù)：9 Pages

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3.3 V Communications Clock PLL

Description The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o

文件：125.94 Kbytes 頁數(shù)：10 Pages

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3.3V Communications Clock PLL

Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.

文件：182.72 Kbytes 頁數(shù)：9 Pages

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3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20 pin SOIC ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz ? Locks to

文件：410.92 Kbytes 頁數(shù)：11 Pages

RENESAS

瑞薩

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20-pin SOIC ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz ? Locks to

文件：262.81 Kbytes 頁數(shù)：11 Pages

RENESAS

瑞薩

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20-pin SOIC ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz ? Locks to

文件：262.81 Kbytes 頁數(shù)：11 Pages

RENESAS

瑞薩

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20-pin SOIC ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz ? Locks to

文件：262.81 Kbytes 頁數(shù)：11 Pages

RENESAS

瑞薩

絲?。?a target="_blank" title="Marking" href="/mk2049-45si/marking.html">MK2049-45SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features ? Packaged in 20 pin SOIC ? 3.3 V + 5 operation ? Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E ? Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz ? Locks to

文件：410.92 Kbytes 頁數(shù)：11 Pages

RENESAS

瑞薩

3.3V Communications Clock PLL

Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.

文件：182.72 Kbytes 頁數(shù)：9 Pages

ICST

3.3V Communications Clock PLL

Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.

文件：182.72 Kbytes 頁數(shù)：9 Pages

ICST