5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

文件：133.68 Kbytes 頁(yè)數(shù)：8 Pages

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5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

文件：133.68 Kbytes 頁(yè)數(shù)：8 Pages

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安森美半導(dǎo)體

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

文件：133.68 Kbytes 頁(yè)數(shù)：8 Pages

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3-BIT REGISTERED BUS TRANSCEIVER

The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs (BUS0–BUS2) are specified for driving a 25 ? bus; the receive outputs (Q0 – Q2) are specified for 50 ?. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW,

文件：113.66 Kbytes 頁(yè)數(shù)：4 Pages

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3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER

The MC10E/100E337 is a 3-bit registered bus transceiver with scan. The bus outputs (BUS0–BUS2) are specified for driving a 25 ? bus; the receive outputs (Q0 – Q2) are specified for 50 ?. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW, the outputs go to – 2.0 V

文件：116.81 Kbytes 頁(yè)數(shù)：5 Pages

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QUAD DIFFERENTIAL AND/NAND

The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. T

文件：108.26 Kbytes 頁(yè)數(shù)：4 Pages

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QUAD DIFFERENTIAL AND/NAND

The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. T

文件：108.26 Kbytes 頁(yè)數(shù)：4 Pages

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QUAD DIFFERENTIAL AND/NAND

The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. T

文件：108.26 Kbytes 頁(yè)數(shù)：4 Pages

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QUINT DIFFERENTIAL LINE RECEIVER

Description The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The design incorporates two stages of gain, internal to the device, making it an ex

文件：108.95 Kbytes 頁(yè)數(shù)：4 Pages

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3-BIT DIFFERENTIAL FLIP-FLOP

Description The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output. The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock

文件：109.58 Kbytes 頁(yè)數(shù)：4 Pages

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