4-bit universal shift register

DESCRIPTION The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

文件：77.78 Kbytes 頁數(shù)：8 Pages

PHI

PHI

4-bit universal shift register

DESCRIPTION The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

文件：77.78 Kbytes 頁數(shù)：8 Pages

PHI

PHI

4-bit universal shift register

DESCRIPTION The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

文件：77.78 Kbytes 頁數(shù)：8 Pages

PHI

PHI

4-bit universal shift register

DESCRIPTION The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

文件：77.78 Kbytes 頁數(shù)：8 Pages

PHI

PHI

4-bit universal shift register

DESCRIPTION The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

文件：77.78 Kbytes 頁數(shù)：8 Pages

PHI

PHI

4-bit universal shift register

DESCRIPTION The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

文件：77.78 Kbytes 頁數(shù)：8 Pages

PHI

PHI

4-bit universal shift register

恩XP