Hex / Quadruple D-type Flip-Flops (with clear)

Hex / Quadruple D-type Flip-Flops (with clear) These positive-edge-triggered flip-flops utilize TTL circuitry toimplement D-type flip-flop logic. All have a direct clear input, and the HD74LS175 features complementary outputs from each flip-flops. Information at the D inputs meeting the se

文件：112.87 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩

Hex / Quadruple D-type Flip-Flops (with clear)

Hex / Quadruple D-type Flip-Flops (with clear) These positive-edge-triggered flip-flops utilize TTL circuitry toimplement D-type flip-flop logic. All have a direct clear input, and the HD74LS175 features complementary outputs from each flip-flops. Information at the D inputs meeting the se

文件：112.87 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩

LOW POWER SCHOTTKY

The LSTTL/MSI SN74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops.

文件：104.94 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：318.44 Kbytes 頁數(shù)：7 Pages

TI

德州儀器