Octal D-type Positive-edge-triggered Flip-Flops (with Clear)

The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the cl

文件：98.24 Kbytes 頁數(shù)：7 Pages

RENESAS

瑞薩

General-Purpose Logics-HD74LS Series

Renesas

瑞薩

Octal D-type Positive-edge-triggered Flip-Flops (with Clear)

The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the cl

文件：98.24 Kbytes 頁數(shù)：7 Pages

RENESAS

瑞薩

OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP WITH RESET

文件：210.88 Kbytes 頁數(shù)：4 Pages

MITSUBISHI

三菱電機

LOW POWER SCHOTTKY

The SN74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. ? 8-Bit High Speed Register ? Parallel Register ? Common C

文件：117.18 Kbytes 頁數(shù)：8 Pages

ONSEMI

安森美半導(dǎo)體