a high-density CMOS device

Overview The DSP56374 is a high-density CMOS device with 3.3 V inputs and outputs. The DSP56374 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high performance, single-clock-per-cycle DSP5

文件：1.12936 Mbytes 頁數(shù)：64 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導體

high density CMOS device with 3.3 V inputs and outputs

Overview The DSP56374 is a high density CMOS device with 3.3 V inputs and outputs. The DSP56374 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high performance, single-clock-per-cycle DSP5

文件：1.71302 Mbytes 頁數(shù)：128 Pages

MOTOROLA

摩托羅拉

24-BIT DIGITAL SIGNAL PROCESSOR

24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56307, a member of the DSP56300 family of programmable digital signal processors (DSPs), supports wireless infrastructure applications with general filtering operations. The on-chip enhanced filter coprocessor (EFCOP) processes filter algorithms in

文件：947.84 Kbytes 頁數(shù)：156 Pages

MOTOROLA

摩托羅拉

24-Bit Digital Signal Processor

Features ? 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 頁數(shù)：124 Pages

恩XP

DSP56307EVM Evaluation Module

FEATURES Hardware ? 24-bit DSP56307 Digital Signal Processor – High -Performance DSP56300 core ? 100 Million Instructions Per Second (MIPS) with a 100-MHz clock at 2.5-V core and 3.3 V I/O ? Object code compatible with the DSP56000 core ? Highly-parallel instruction set ? Data Arithmetic L

文件：246.29 Kbytes 頁數(shù)：8 Pages

恩XP

24-Bit Digital Signal Processor

DSP56321T Features High-Performance DSP56300 Core ? 220/240 million multiply-accumulates per second (MMACS) (440/480 MMACS using the EFCOP in filtering applications) with a 220/240 MHz clock at 1.6 V core and 3.3 V I/O and a junction temperature range of 0–85°C ? Object code compatible with t

文件：2.1632 Mbytes 頁數(shù)：88 Pages

恩XP

24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core ? 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 ′ 24-bit parallel M

文件：2.86554 Mbytes 頁數(shù)：120 Pages

恩XP

24-BIT DIGITAL SIGNAL PROCESSOR

FEATURES High-Performance DSP56300 Core ￥ 100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and 3.3 V I/O ￥ Object code compatible with the DSP56000 core ￥ Highly parallel instruction set ￥ Data arithmetic logic unit (ALU) D Fully pipelined 24 x 24-bit parallel m

文件：1.83703 Mbytes 頁數(shù)：156 Pages

恩XP

24-Bit Digital Signal Processor

Features ? 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 頁數(shù)：124 Pages

恩XP

24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core ? 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 ′ 24-bit parallel M

文件：2.86554 Mbytes 頁數(shù)：120 Pages

恩XP