DSP56303 USER?? MANUAL

This manual describes the DSP56303 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56303 is an implementation of the DSP56300 core with a unique configuration of internal memory, cache, and peripherals.

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FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core ? 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit para

文件：2.34958 Mbytes 頁數(shù)：108 Pages

恩XP

24-Bit Digital Signal Processor

文件：2.39074 Mbytes 頁數(shù)：108 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體

24-bit General Embedded DSP

Overview The DSP56303 is intended for use in telecommunication applications, such as multi-line voice/data/fax processing, videoconferencing, audio applications, control, and general digital signal processing.?\nThe DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal High performance DSP56300 core\n\n\n\n?100 million multiply-accumulates per second (MMACS) with a 100 MHz clock\n\n\n?Object code compatible with the DSP56000 core\n\n\n?Highly parallel instruction set\n\n\n?Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)\n\n\n?56-bit parallel barr;

恩XP

24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core ? 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit para

文件：2.34958 Mbytes 頁數(shù)：108 Pages

恩XP

24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core ? 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit para

文件：2.34958 Mbytes 頁數(shù)：108 Pages

恩XP

24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core ? 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit para

文件：2.34958 Mbytes 頁數(shù)：108 Pages

恩XP

24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core ? 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit para

文件：2.34958 Mbytes 頁數(shù)：108 Pages

恩XP

24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core ? 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal ? Object code compatible with the DSP56000 core with highly parallel instruction set ? Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit para

文件：2.34958 Mbytes 頁數(shù)：108 Pages

恩XP

24-Bit Digital Signal Processor

文件：2.39074 Mbytes 頁數(shù)：108 Pages

FREESCALEFreescale Semiconductor, Inc

飛思卡爾飛思卡爾半導(dǎo)體