絲印：CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁(yè)數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：160.08 Kbytes 頁(yè)數(shù)：11 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁(yè)數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2510A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to Four Banks of Four Outputs Separate Output Enable for Each Output Bank External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the

文件：569.86 Kbytes 頁(yè)數(shù)：18 Pages

TI

德州儀器