3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

文件：350.98 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：170.14 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

絲印：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

文件：350.98 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

絲印：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

文件：350.98 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

絲印：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

文件：350.98 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

絲?。?strong>CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

文件：350.98 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

絲?。?strong>CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

文件：350.98 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

具有 1/2x、1x 和 2x 頻率選項的 100MHz、3.3V PLL 時鐘驅動器

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors ope ? Low-Output Skew for Clock-Distribution and Clock-Generation Applications\n? Distributes One Clock Input to Six Outputs\n? No External RC Network Required\n? Application for Synchronous DRAM, High-Speed Microprocessor\n? TTL-Compatible Inputs and Outputs\n? State-of-the-Art EPIC-IIB? BiCMOS Design ;

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：295.53 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：170.14 Kbytes 頁數(shù)：12 Pages

TI

德州儀器