LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

文件：626.57 Kbytes 頁數(shù)：18 Pages

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德州儀器

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT

文件：333.02 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

Low Jitter Clock Multiplier

文件：613.03 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

Low Jitter Clock Multiplier

文件：613.03 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

文件：626.57 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

Low Jitter Clock Multiplier

文件：613.03 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

Low Jitter Clock Multiplier

文件：613.03 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

文件：626.57 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

Low Jitter Clock Multiplier

文件：613.03 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

具有可編程延遲和相位對(duì)齊的低抖動(dòng)時(shí)鐘倍頻器和分頻器

The CDC5801A device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB fr ? Low Jitter Clock Multiplier by x4, x6, x8. Input Frequency Range (19 MHz to 125 MHz). Supports Output Frequency From 150 MHz to 500 MHz\n? Fail-Safe Power Up Initialization\n? Low Jitter Clock Divider by /2, /3, /4. Input Frequency Range (50 MHz to 125 MHz). Supports Ranges of Output Frequency Fro;

TI

德州儀器