CDx4HC11 Triple 3-Input AND Gates

1 Features ? Buffered inputs ? Wide operating voltage range: 2 V to 6 V ? Wide operating temperature range: –55°C to +125°C ? Supports fanout up to 10 LSTTL loads ? Significant power reduction compared to LSTTL logic ICs 2 Applications ? Combining power good signals ? Enable digital si

文件：1.20587 Mbytes 頁數(shù)：26 Pages

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德州儀器

High Speed CMOS Logic Triple 3-Input AND Gate

文件：33.84 Kbytes 頁數(shù)：6 Pages

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德州儀器

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes 頁數(shù)：11 Pages

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德州儀器

3 通道、3 輸入、2V 至 6V 與門

This device contains three independent 3-input AND gates. Each gate performs the Boolean function Y?=?A?●?B ●?C in positive logic. ? Buffered inputs\n? Wide operating voltage range: 2?V?to?6?V\n? Wide operating temperature range: –55°C?to?+125°C\n? Supports fanout up to 10 LSTTL loads\n? Significant power reduction compared to LSTTL logic ICs;

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德州儀器

CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

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德州儀器

絲印：CD74HC112E；Package：PDIP；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/hc112m/marking.html">HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/hc112m/marking.html">HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/hc112m/marking.html">HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

絲印：HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器