CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

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德州儀器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes 頁數(shù)：20 Pages

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德州儀器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：55.1 Kbytes 頁數(shù)：8 Pages

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德州儀器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes 頁數(shù)：13 Pages

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德州儀器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes 頁數(shù)：18 Pages

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德州儀器

具有設(shè)置和復位端的高速 CMOS 邏輯雙路負邊沿觸發(fā)式 J-K 觸發(fā)器

The ?HC112 and ?HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Set, Reset, a ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n? Complementary Outputs\n? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n? Standard Outputs . . . . . 10 LSTTL Loads\n? Wide Operating Temperature Range . . . –55°C to 125°C\n? Significant Pow;

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德州儀器

絲?。?a target="_blank" title="Marking" href="/cd74hc112e/marking.html">CD74HC112E；Package：PDIP；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

絲印：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/hc112m/marking.html">HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/hc112m/marking.html">HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous set and reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard output

文件：1.3793 Mbytes 頁數(shù)：29 Pages

TI

德州儀器