| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲?。?a target="_blank" title="Marking" href="/cd4517be/marking.html">CD4517BE；Package：PDIP；CMOS Dual 64-Stage Static Shift Register Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads 文件：475.92 Kbytes 頁(yè)數(shù)：11 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4517bf3a/marking.html">CD4517BF3A；Package：CDIP；CMOS Dual 64-Stage Static Shift Register Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads 文件：475.92 Kbytes 頁(yè)數(shù)：11 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4517bf3a/marking.html">CD4517BF3A；Package：CDIP；CMOS Dual 64-Stage Static Shift Register Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads 文件：475.92 Kbytes 頁(yè)數(shù)：11 Pages | TI 德州儀器 | TI | ||
CMOS Dual 64-Stage Static Shift Register Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads 文件：475.92 Kbytes 頁(yè)數(shù)：11 Pages | TI 德州儀器 | TI | ||
CMOS Dual 64-Stage Static Shift Register Description CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted 文件：116.61 Kbytes 頁(yè)數(shù)：9 Pages | INTERSIL | INTERSIL | ||
CMOS Dual Up Counters Description CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-g 文件：112.68 Kbytes 頁(yè)數(shù)：10 Pages | INTERSIL | INTERSIL | ||
CMOS Dual Up-Counters Features: Medium-speed operation — 6-MHz typical clock frequency st 10 V, = Positive- or negative-edge triggering m Synchronous internal carry propagation . 100% tested for quiescent current at 20 V & Maximum input current of 1 uA at 18 V ‘over full package-temperature range; 100 nAat 文件：986.41 Kbytes 頁(yè)數(shù)：22 Pages | TI 德州儀器 | TI | ||
絲印：CD4518BE；Package：PDIP；CMOS Dual Up-Counters Features: Medium-speed operation — 6-MHz typical clock frequency st 10 V, = Positive- or negative-edge triggering m Synchronous internal carry propagation . 100% tested for quiescent current at 20 V & Maximum input current of 1 uA at 18 V ‘over full package-temperature range; 100 nAat 文件：986.41 Kbytes 頁(yè)數(shù)：22 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4518be/marking.html">CD4518BE；Package：PDIP；CMOS Dual Up-Counters Features: Medium-speed operation — 6-MHz typical clock frequency st 10 V, = Positive- or negative-edge triggering m Synchronous internal carry propagation . 100% tested for quiescent current at 20 V & Maximum input current of 1 uA at 18 V ‘over full package-temperature range; 100 nAat 文件：986.41 Kbytes 頁(yè)數(shù)：22 Pages | TI 德州儀器 | TI | ||
絲印：CD4518BE；Package：PDIP；CMOS Dual Up-Counters Features: Medium-speed operation — 6-MHz typical clock frequency st 10 V, = Positive- or negative-edge triggering m Synchronous internal carry propagation . 100% tested for quiescent current at 20 V & Maximum input current of 1 uA at 18 V ‘over full package-temperature range; 100 nAat 文件：986.41 Kbytes 頁(yè)數(shù)：22 Pages | TI 德州儀器 | TI |
詳細(xì)參數(shù)
- 型號(hào)：
CD451
- 功能描述：
編碼器、解碼器、復(fù)用器和解復(fù)用器 Latch/Decoder/Driver
- RoHS：
否
- 制造商：
Micrel
- 產(chǎn)品：
Multiplexers
- 邏輯系列：
CMOS
- 線路數(shù)量（輸入/輸出）：
2/12
- 傳播延遲時(shí)間：
350 ps, 400 ps
- 電源電壓-最大：
2.625 V, 3.6 V
- 電源電壓-最?。?/span>
2.375 V, 3 V
- 最大工作溫度：
+ 85 C
- 安裝風(fēng)格：
SMD/SMT
- 封裝/箱體：
QFN-44
- 封裝：
Tray
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
FUJSITSU |
25+ |
SOP16 |
2500 |
強(qiáng)調(diào)現(xiàn)貨,隨時(shí)查詢! |
詢價(jià) | ||
FAIRCHILD |
24+ |
16P |
363 |
詢價(jià) | |||
REI |
16+ |
原廠封裝 |
10000 |
全新原裝正品,代理優(yōu)勢(shì)渠道供應(yīng),歡迎來(lái)電咨詢 |
詢價(jià) | ||
NSC |
25+ |
SOP16 |
2650 |
原裝優(yōu)勢(shì)!絕對(duì)公司現(xiàn)貨 |
詢價(jià) | ||
FSC |
25+23+ |
SMD |
41801 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
FAIRCHILD/仙童 |
23+ |
SOP |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
FAIRC |
23+ |
105 |
現(xiàn)貨庫(kù)存 |
詢價(jià) | |||
FIN |
2025+ |
SOP16 |
3365 |
全新原廠原裝產(chǎn)品、公司現(xiàn)貨銷(xiāo)售 |
詢價(jià) | ||
FUJSITSU |
00+ |
SOP16 |
495 |
原裝現(xiàn)貨 |
詢價(jià) | ||
FAIRCHILD/仙童 |
25+ |
SOP-16 |
266 |
原裝正品,假一罰十! |
詢價(jià) |
相關(guān)規(guī)格書(shū)
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相關(guān)庫(kù)存
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- CD4514BMJ883B
- CD4514BPWR
- CD4515BC
- CD4515BCN
- CD4515BCWMX
- CD4515BD3
- CD4515BEE4
