Quad And/Or Select Gate

I-CORE

中微愛芯

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

文件：74.66 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Description CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each con sist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter. ?

文件：149.61 Kbytes 頁數(shù)：12 Pages

INTERSIL

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

文件：74.66 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

文件：74.66 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

絲?。?a target="_blank" title="Marking" href="/cd40192be/marking.html">CD40192BE；Package：PDIP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd40192be/marking.html">CD40192BE；Package：PDIP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd40192bf/marking.html">CD40192BF；Package：CDIP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲印：CD40192BF；Package：CDIP；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

文件：915.5 Kbytes 頁數(shù)：20 Pages

TI

德州儀器