CMOS NOR Gates

文件：206.27 Kbytes 頁數(shù)：5 Pages

TI

德州儀器

Dual 4-Input NOR(NAND) Gate

文件：107.87 Kbytes 頁數(shù)：6 Pages

NSC

國半

2路4輸入或非門

The CD4002 is a dual 4-input NOR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS ? Wide supply voltage range from 3V to 15V\n? Fully static operation\n? 5V, 10V, and 15V parametric ratings\n? Standardized symmetrical output characteristics\n? Inputs and outputs are protected against electrostatic effects\n? Specified from -40℃ to +105℃\n? Packaging information: DIP14/SOP14/TSSOP;

I-CORE

中微愛芯

CD4002M/CD4002C Dual 4-Input NOR Gate, CD4012M/CD4012C Dual 4-Input NAND Gate

General Description\nThese NOR and NAND gates are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide suppl Wide supply voltage range 3.0V to 15V\nLow power 10 nW (typ.)\nHigh noise immunity 0.45 VDD (typ.)Applications\nAutomotive\nData terminals\nInstrumentation\nMedical Electronics\nAlarm system\nIndustrial controls\nRemote metering\nComputers;

TI

德州儀器

CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ? 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

文件：1.02076 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4002be/marking.html">CD4002BE；Package：PDIP；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ? 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

文件：1.02076 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ? 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

文件：1.02076 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4002be/marking.html">CD4002BE；Package：PDIP；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ? 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

文件：1.02076 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ? 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

文件：1.02076 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4002bf/marking.html">CD4002BF；Package：CDIP；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ? 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

文件：1.02076 Mbytes 頁數(shù)：23 Pages

TI

德州儀器