Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 頁(yè)數(shù)：16 Pages

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雙路輸出網(wǎng)絡(luò)時(shí)鐘發(fā)生器

AD9575是一款高度集成的雙路輸出時(shí)鐘發(fā)生器，包括一個(gè)針對(duì)網(wǎng)絡(luò)定時(shí)而優(yōu)化的片內(nèi)PLL內(nèi)核。整數(shù)N分頻PLL設(shè)計(jì)基于ADI公司成熟的高性能、低抖動(dòng)頻率合成器系列，可實(shí)現(xiàn)線路卡的較高性能。對(duì)相位噪聲和抖動(dòng)要求苛刻的其它應(yīng)用也能受益于該器件。????????? PLL部分由低噪聲鑒頻鑒相器(PFD)、精密電荷泵、低相位噪聲壓控振蕩器(VCO)和引腳可選的反饋與輸出分頻器組成。通過(guò)連接一個(gè)外部晶振，可以將常用的網(wǎng)絡(luò)輸出頻率鎖定至輸入?yún)⒖?。輸出分頻比和反饋分頻比可針對(duì)所要求的輸出速率，通過(guò)引腳進(jìn)行編程。無(wú)需外部環(huán)路濾波器，從而節(jié)省寶貴的設(shè)計(jì)時(shí)間和電路板空間。\n\n?? AD957 ? 完全集成的VCO/PLL內(nèi)核\n\n? 均方根抖動(dòng)：0.39 ps（12 kHz至20 MHz，156.25 MHz）\n\n? 均方根抖動(dòng)：0.15 ps（1.875 MHz至20 MHz，156.25 MHz）\n\n? 均方根抖動(dòng)：0.40 ps（12 kHz至20 MHz，106.25 MHz）\n\n? 均方根抖動(dòng)：0.15 ps（637 kHz至10 MHz，106.25 MHz）;

ADI

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Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 頁(yè)數(shù)：16 Pages

AD

亞德諾

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 頁(yè)數(shù)：16 Pages

AD

亞德諾

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 頁(yè)數(shù)：16 Pages

AD

亞德諾

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 頁(yè)數(shù)：16 Pages

AD

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Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：托盤(pán) 類別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：IC PLL CLOCK GEN 25MHZ 16TSSOP

AD

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Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：托盤(pán) 類別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：IC PLL CLOCK GEN 25MHZ 16TSSOP

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