Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 頁數(shù)：16 Pages

AD

亞德諾

Package：16-TSSOP（0.173"，4.40mm 寬）；包裝：托盤 類別：集成電路（IC） 應用特定時鐘/定時 描述：IC PLL CLOCK GEN 25MHZ 16TSSOP

AD

亞德諾

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 頁數(shù)：16 Pages

AD

亞德諾

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 頁數(shù)：16 Pages

AD

亞德諾

P-Channel 60-V (D-S) MOSFET

文件：988.33 Kbytes 頁數(shù)：8 Pages

VBSEMI

微碧半導體